From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F2BDC83000 for ; Tue, 28 Apr 2020 18:02:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3A8EA206A1 for ; Tue, 28 Apr 2020 18:02:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="n4Tz0ZPj" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728558AbgD1SCT (ORCPT ); Tue, 28 Apr 2020 14:02:19 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:57600 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727827AbgD1R7R (ORCPT ); Tue, 28 Apr 2020 13:59:17 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=Content-Transfer-Encoding:MIME-Version:Message-Id:Date:Subject: Cc:To:From:Sender:Reply-To:Content-Type:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: In-Reply-To:References:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=XQSu7TMEXytJWHO15QNLftQ1/MdjNcFx1sEuUg1XFLo=; b=n4Tz0ZPj4nmCk1r+b57GzrU7WK 4mJONiMAoABdMKwpHMOfVpZgMMCqxJpmbz3shJPyWCN5BKX3aRwBXQ5cvtXSZE6CbKmZjlSRW4/I5 OeW7KygoDN1EnT6uok2gsC5X6Av4RPRoS5AprXrI1jbpegQCPD6SzrJKXO0/3oUyRx0Y=; Received: from andrew by vps0.lunn.ch with local (Exim 4.93) (envelope-from ) id 1jTUVk-0007xP-Nd; Tue, 28 Apr 2020 19:59:12 +0200 From: Andrew Lunn To: David Miller Cc: netdev , Chris Healy , Andy Duan , Leonard Crestez , Andrew Lunn Subject: [PATCH net-next] net: ethernet: fec: Prevent MII event after MII_SPEED write Date: Tue, 28 Apr 2020 19:58:33 +0200 Message-Id: <20200428175833.30517-1-andrew@lunn.ch> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The change to polled IO for MDIO completion assumes that MII events are only generated for MDIO transactions. However on some SoCs writing to the MII_SPEED register can also trigger an MII event. As a result, the next MDIO read has a pending MII event, and immediately reads the data registers before it contains useful data. When the read does complete, another MII event is posted, which results in the next read also going wrong, and the cycle continues. By writing 0 to the MII_DATA register before writing to the speed register, this MII event for the MII_SPEED is suppressed, and polled IO works as expected. Fixes: 29ae6bd1b0d8 ("net: ethernet: fec: Replace interrupt driven MDIO with polled IO") Reported-by: Andy Duan Suggested-by: Andy Duan Signed-off-by: Andrew Lunn --- drivers/net/ethernet/freescale/fec_main.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c index 1ae075a246a3..aa5e744ec098 100644 --- a/drivers/net/ethernet/freescale/fec_main.c +++ b/drivers/net/ethernet/freescale/fec_main.c @@ -996,6 +996,9 @@ fec_restart(struct net_device *ndev) writel(0x0, fep->hwp + FEC_X_CNTRL); } + /* Prevent an MII event being report when changing speed */ + writel(0, fep->hwp + FEC_MII_DATA); + /* Set MII speed */ writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); @@ -1182,6 +1185,10 @@ fec_stop(struct net_device *ndev) writel(val, fep->hwp + FEC_ECNTRL); fec_enet_stop_mode(fep, true); } + + /* Prevent an MII event being report when changing speed */ + writel(0, fep->hwp + FEC_MII_DATA); + writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); /* We have to keep ENET enabled to have MII interrupt stay working */ @@ -2142,6 +2149,16 @@ static int fec_enet_mii_init(struct platform_device *pdev) if (suppress_preamble) fep->phy_speed |= BIT(7); + /* Clear MMFR to avoid to generate MII event by writing MSCR. + * MII event generation condition: + * - writing MSCR: + * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & + * mscr_reg_data_in[7:0] != 0 + * - writing MMFR: + * - mscr[7:0]_not_zero + */ + writel(0, fep->hwp + FEC_MII_DATA); + writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); /* Clear any pending transaction complete indication */ -- 2.26.1