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From: Andrew Lunn <andrew@lunn.ch>
To: Helmut Grohne <helmut.grohne@intenta.de>
Cc: Florian Fainelli <f.fainelli@gmail.com>,
	Heiner Kallweit <hkallweit1@gmail.com>,
	Russell King <linux@armlinux.org.uk>,
	"David S. Miller" <davem@davemloft.net>,
	Jakub Kicinski <kuba@kernel.org>,
	netdev@vger.kernel.org, Woojung Huh <woojung.huh@microchip.com>,
	Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>,
	Vivien Didelot <vivien.didelot@gmail.com>,
	Tristram Ha <Tristram.Ha@microchip.com>
Subject: Re: [PATCH v3] net: dsa: microchip: call phy_remove_link_mode during probe
Date: Mon, 20 Jul 2020 23:04:49 +0200	[thread overview]
Message-ID: <20200720210449.GP1339445@lunn.ch> (raw)
In-Reply-To: <20200720090416.GA7307@laureti-dev>

> The dev->ports[i].phydev is not actually exposed beyond the driver. The
> driver sets the phydev.speed in a few places and even reads it back in
> one place. It also sets phydev.duplex, but never reads it back. It
> queries phydev.link, which is statically 0 due to using devm_kzalloc.
> 
> I think the use of this ksz_port.phydev is very misleading, but I'm
> unsure how to fix this. It is not clear to me whether all those updates
> should be performed on the connected phydev instead or whether this is
> just internal state tracking.

I took a quick look at the code.

For PHY addresses < dev->phy_port_cnt it passes all reads/writes
through to the hardware. So the Linux MDIO/PHY subsystem will be able
to fully drive these PHYs, and the ksz9477 internal phydev is
unneeded.

Where it gets interesting is addr >= dev->phy_port_cnt. Reads of the
PHY registers return hard coded values, or the link speed from the
local phydev. Writes to these registers are just ignored.

If you compare this to other DSA drivers/DSA switches, reads/write for
addresses where there are no internal PHY get passed out to an
external MDIO bus, where an external PHY can be connected. The Linux
MDIO/PHY subsystem will discover these external PHYs and create phydev
instance for them. If there is no external PHY, for example the MAC is
connected to another MAC, no PHY will be detected, and fixed-link is
used in its place.

Do these switches have an external MDIO bus?
How are external PHYs usually managed?

At a minimum, the internal phydev can be replaced with just a speed,
rather than a full phydev, which will reduce confusion. But it would
be nice to go further and remove all the addr >= dev->phy_port_cnt
handling. But we need to understand the implications of that.

	Andrew

  parent reply	other threads:[~2020-07-20 21:04 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-14  8:25 [PATCH] net: phy: phy_remove_link_mode should not advertise new modes Helmut Grohne
2020-07-14 21:07 ` David Miller
2020-07-15  7:03   ` Helmut Grohne
2020-07-15 18:20     ` Jakub Kicinski
2020-07-15 19:01       ` Andrew Lunn
2020-07-15 18:51     ` Andrew Lunn
2020-07-15 19:27 ` Andrew Lunn
2020-07-16 12:57   ` [PATCH v2] net: dsa: microchip: call phy_remove_link_mode during probe Helmut Grohne
2020-07-16 14:10     ` Andrew Lunn
2020-07-17  8:18       ` Helmut Grohne
2020-07-17 13:18         ` Andrew Lunn
2020-07-20  9:04           ` [PATCH v3] " Helmut Grohne
2020-07-20 20:43             ` Andrew Lunn
2020-07-21 11:07               ` [PATCH v4] " Helmut Grohne
2020-07-21 15:20                 ` Andrew Lunn
2020-07-21 22:50                 ` David Miller
2020-07-20 21:04             ` Andrew Lunn [this message]
2020-07-21  7:38               ` [PATCH v3] " Helmut Grohne

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