From: Andrew Lunn <andrew@lunn.ch>
To: Marek Vasut <marex@denx.de>
Cc: netdev@vger.kernel.org,
Christoph Niedermaier <cniedermaier@dh-electronics.com>,
"David S . Miller" <davem@davemloft.net>,
NXP Linux Team <linux-imx@nxp.com>,
Richard Leitner <richard.leitner@skidata.com>,
Shawn Guo <shawnguo@kernel.org>
Subject: Re: [PATCH] net: fec: Fix PHY init after phy_reset_after_clk_enable()
Date: Thu, 3 Sep 2020 23:53:31 +0200 [thread overview]
Message-ID: <20200903215331.GG3112546@lunn.ch> (raw)
In-Reply-To: <b6397b39-c897-6e0a-6bf7-b6b24908de1a@denx.de>
On Thu, Sep 03, 2020 at 11:36:39PM +0200, Marek Vasut wrote:
> On 9/3/20 11:00 PM, Andrew Lunn wrote:
> > On Thu, Sep 03, 2020 at 10:27:12PM +0200, Marek Vasut wrote:
> >> The phy_reset_after_clk_enable() does a PHY reset, which means the PHY
> >> loses its register settings. The fec_enet_mii_probe() starts the PHY
> >> and does the necessary calls to configure the PHY via PHY framework,
> >> and loads the correct register settings into the PHY. Therefore,
> >> fec_enet_mii_probe() should be called only after the PHY has been
> >> reset, not before as it is now.
> >
> > I think this patch is related to what Florian is currently doing with
> > PHY clocks.
>
> Which is what ? Details please.
Have you used b4 before?
b4 am 20200903043947.3272453-1-f.fainelli@gmail.com
> > I think a better fix for the original problem is for the SMSC PHY
> > driver to control the clock itself. If it clk_prepare_enables() the
> > clock, it knows it will not be shut off again by the FEC run time
> > power management.
>
> The FEC MAC is responsible for generating the clock, the PHY clock are
> not part of the clock framework as far as I can tell.
I'm not sure this is true. At least:
https://elixir.bootlin.com/linux/latest/source/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi#L123
and there are a few more examples:
imx6ul-14x14-evk.dtsi: clocks = <&clks IMX6UL_CLK_ENET_REF>;
imx6ul-kontron-n6x1x-s.dtsi: clocks = <&clks IMX6UL_CLK_ENET_REF>;
imx6ul-kontron-n6x1x-som-common.dtsi: clocks = <&clks IMX6UL_CLK_ENET_REF>;
imx6ull-myir-mys-6ulx.dtsi: clocks = <&clks IMX6UL_CLK_ENET_REF>;
imx6ul-phytec-phycore-som.dtsi: clocks = <&clks IMX6UL_CLK_ENET_REF>;
Maybe it is just IMX6?
Andrew
next prev parent reply other threads:[~2020-09-03 21:53 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-03 20:27 [PATCH] net: fec: Fix PHY init after phy_reset_after_clk_enable() Marek Vasut
2020-09-03 21:00 ` Andrew Lunn
2020-09-03 21:36 ` Marek Vasut
2020-09-03 21:53 ` Andrew Lunn [this message]
2020-09-03 22:03 ` Marek Vasut
2020-09-03 22:08 ` Andrew Lunn
2020-09-03 22:45 ` Marek Vasut
2020-09-04 14:02 ` Andrew Lunn
2020-09-04 15:26 ` Marek Vasut
2020-09-04 19:02 ` Richard Leitner
2020-09-04 19:23 ` Marek Vasut
2020-09-09 8:38 ` Richard Leitner
2020-09-26 18:52 ` Marek Vasut
2020-09-28 13:03 ` Richard Leitner
2020-10-06 9:15 ` Marek Vasut
2020-09-09 12:24 ` Andrew Lunn
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