From: Pavel Machek <pavel@denx.de>
To: Min Li <min.li.xe@renesas.com>
Cc: "richardcochran@gmail.com" <richardcochran@gmail.com>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH net 1/4] ptp: ptp_idt82p33: update to support adjphase
Date: Sat, 17 Oct 2020 12:33:54 +0200 [thread overview]
Message-ID: <20201017103354.GA4607@amd> (raw)
In-Reply-To: <OSAPR01MB178028345EC84C1564DD104ABA020@OSAPR01MB1780.jpnprd01.prod.outlook.com>
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Hi!
> +static int idt82p33_adjwritephase(struct ptp_clock_info *ptp, s32
> +offsetNs) {
adj_write_phase?
> + struct idt82p33_channel *channel =
> + container_of(ptp, struct idt82p33_channel, caps);
> + struct idt82p33 *idt82p33 = channel->idt82p33;
> + s64 offsetInFs;
> + s64 offsetRegVal;
> + u8 val[4] = {0};
> + int err;
> +
> + offsetInFs = (s64)(-offsetNs) * 1000000;
> +
> + if (offsetInFs > WRITE_PHASE_OFFSET_LIMIT)
> + offsetInFs = WRITE_PHASE_OFFSET_LIMIT;
> + else if (offsetInFs < -WRITE_PHASE_OFFSET_LIMIT)
> + offsetInFs = -WRITE_PHASE_OFFSET_LIMIT;
I'm sure we have macro for this.
> + /* Convert from phaseOffsetInFs to register value */
> + offsetRegVal = ((offsetInFs * 1000) / IDT_T0DPLL_PHASE_RESOL);
> +
> + val[0] = offsetRegVal & 0xFF;
> + val[1] = (offsetRegVal >> 8) & 0xFF;
> + val[2] = (offsetRegVal >> 16) & 0xFF;
> + val[3] = (offsetRegVal >> 24) & 0x1F;
> + val[3] |= PH_OFFSET_EN;
ThisIsReally far away from usual coding style.
Best regards,
Pavel
--
http://www.livejournal.com/~pavelmachek
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prev parent reply other threads:[~2020-10-17 10:34 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-07 15:55 [PATCH net 1/4] ptp: ptp_idt82p33: update to support adjphase min.li.xe
2020-08-07 20:56 ` kernel test robot
2020-08-07 21:57 ` kernel test robot
2020-10-15 19:30 ` Min Li
2020-10-15 21:23 ` Richard Cochran
2020-10-17 10:33 ` Pavel Machek [this message]
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