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From: Xu Yilun <yilun.xu@intel.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: jesse.brandeburg@intel.com, anthony.l.nguyen@intel.com,
	davem@davemloft.net, kuba@kernel.org, mdf@kernel.org,
	lee.jones@linaro.org, linux-kernel@vger.kernel.org,
	linux-fpga@vger.kernel.org, netdev@vger.kernel.org,
	trix@redhat.com, lgoncalv@redhat.com, hao.wu@intel.com,
	yilun.xu@intel.com
Subject: Re: [RFC PATCH 1/6] docs: networking: add the document for DFL Ether Group driver
Date: Mon, 2 Nov 2020 10:38:09 +0800	[thread overview]
Message-ID: <20201102023809.GA10673@yilunxu-OptiPlex-7050> (raw)
In-Reply-To: <20201026191400.GO752111@lunn.ch>

Hi Andrew:

On Mon, Oct 26, 2020 at 08:14:00PM +0100, Andrew Lunn wrote:
> > > > > Do you really mean PHY? I actually expect it is PCS? 
> > > > 
> > > > For this implementation, yes.
> > > 
> > > Yes, you have a PHY? Or Yes, it is PCS?
> > 
> > Sorry, I mean I have a PHY.
> > 
> > > 
> > > To me, the phylib maintainer, having a PHY means you have a base-T
> > > interface, 25Gbase-T, 40Gbase-T?  That would be an odd and expensive
> > > architecture when you should be able to just connect SERDES interfaces
> > > together.
> 
> You really have 25Gbase-T, 40Gbase-T? Between the FPGA & XL710?
> What copper PHYs are using? 
> 
> > I see your concerns about the SERDES interface between FPGA & XL710.
> 
> I have no concerns about direct SERDES connections. That is the normal
> way of doing this. It keeps it a lot simpler, since you don't have to
> worry about driving the PHYs.
>

I did some investigation and now I have some details.
The term 'PHY' described in Ether Group Spec should be the PCS + PMA, a figure
below for one configuration:

 +------------------------+          +-----------------+
 | Host Side Ether Group  |          |      XL710      |
 |                        |          |                 |
 | +--------------------+ |          |                 |
 | | 40G Ether IP       | |          |                 |
 | |                    | |          |                 |
 | |       +---------+  | |  XLAUI   |                 |
 | | MAC - |PCS - PMA|  | |----------| PMA - PCS - MAC |
 | |       +---------+  | |          |                 |
 +-+--------------------+-+          +-----------------+

Thanks,
Yilun

  parent reply	other threads:[~2020-11-02  2:43 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-23  8:45 [RFC PATCH 0/6] Add the netdev support for Intel PAC N3000 FPGA Xu Yilun
2020-10-23  8:45 ` [RFC PATCH 1/6] docs: networking: add the document for DFL Ether Group driver Xu Yilun
2020-10-23 15:37   ` Andrew Lunn
2020-10-26  8:52     ` Xu Yilun
2020-10-26 13:00       ` Andrew Lunn
2020-10-26 17:38         ` Xu Yilun
2020-10-26 18:35           ` Jakub Kicinski
2020-10-27  2:33             ` Xu Yilun
2020-10-26 19:14           ` Andrew Lunn
2020-10-27  3:27             ` Xu Yilun
2020-11-02  2:38             ` Xu Yilun [this message]
2020-11-02 14:46               ` Andrew Lunn
2020-10-24 14:25   ` Tom Rix
2020-10-23  8:45 ` [RFC PATCH 2/6] fpga: dfl: export network configuration info for DFL based FPGA Xu Yilun
2020-10-24 13:59   ` Tom Rix
2020-10-26  3:29   ` Wu, Hao
2020-10-23  8:45 ` [RFC PATCH 3/6] fpga: dfl: add an API to get the base device for dfl device Xu Yilun
2020-10-24 14:39   ` Tom Rix
2020-10-26  3:42   ` Wu, Hao
2020-10-23  8:45 ` [RFC PATCH 4/6] ethernet: m10-retimer: add support for retimers on Intel MAX 10 BMC Xu Yilun
2020-10-24 15:03   ` Tom Rix
2020-10-24 16:39     ` Andrew Lunn
2020-10-24 17:36       ` Tom Rix
2020-10-24 20:33         ` Andrew Lunn
2020-10-23  8:45 ` [RFC PATCH 5/6] ethernet: dfl-eth-group: add DFL eth group private feature driver Xu Yilun
2020-10-24 14:37   ` Andrew Lunn
2020-10-24 17:25   ` Tom Rix
2020-10-25 14:47     ` Andrew Lunn
2020-10-23  8:45 ` [RFC PATCH 6/6] ethernet: dfl-eth-group: add support for the 10G configurations Xu Yilun
2020-10-24 17:43   ` Tom Rix

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