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From: Andrew Lunn <andrew@lunn.ch>
To: Arnd Bergmann <arnd@kernel.org>
Cc: "Jernej Škrabec" <jernej.skrabec@gmail.com>,
	"Ard Biesheuvel" <ardb@kernel.org>,
	"Daniel Thompson" <daniel.thompson@linaro.org>,
	"Sumit Garg" <sumit.garg@linaro.org>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Masami Hiramatsu" <mhiramat@kernel.org>,
	"Steve McIntyre" <steve@einval.com>,
	"open list:BPF JIT for MIPS (32-BIT AND 64-BIT)"
	<netdev@vger.kernel.org>, "Willy Liu" <willy.liu@realtek.com>,
	"David S. Miller" <davem@davemloft.net>,
	"Jakub Kicinski" <kuba@kernel.org>,
	"Sasha Levin" <sashal@kernel.org>,
	"Florian Fainelli" <f.fainelli@gmail.com>,
	"Heiner Kallweit" <hkallweit1@gmail.com>,
	"Masahisa Kojima" <masahisa.kojima@linaro.org>,
	"Ilias Apalodimas" <ilias.apalodimas@linaro.org>
Subject: Re: Re: realtek PHY commit bbc4d71d63549 causes regression
Date: Fri, 13 Nov 2020 17:56:25 +0100
Message-ID: <20201113165625.GN1456319@lunn.ch> (raw)
In-Reply-To: <CAK8P3a2iwwneb+FPuUQRm1JD8Pk54HCPnux4935Ok43WDPRaYQ@mail.gmail.com>

> > Hi Arnd
> >
> > This PHY driver bug hiding DT bug is always hard to handle. We have
> > been though it once before with the Atheros PHY. All the buggy DT
> > files were fixed in about one cycle.
> 
> Do you have a link to the problem for the Atheros PHY?

commit cd28d1d6e52e740130745429b3ff0af7cbba7b2c
Author: Vinod Koul <vkoul@kernel.org>
Date:   Mon Jan 21 14:43:17 2019 +0530

    net: phy: at803x: Disable phy delay for RGMII mode
    
    For RGMII mode, phy delay should be disabled. Add this case along
    with disable delay routines.
    
    Signed-off-by: Vinod Koul <vkoul@kernel.org>
    Signed-off-by: David S. Miller <davem@davemloft.net>

and

commit 6d4cd041f0af5b4c8fc742b4a68eac22e420e28c
Author: Vinod Koul <vkoul@kernel.org>
Date:   Thu Feb 21 15:53:15 2019 +0530

    net: phy: at803x: disable delay only for RGMII mode
    
    Per "Documentation/devicetree/bindings/net/ethernet.txt" RGMII mode
    should not have delay in PHY whereas RGMII_ID and RGMII_RXID/RGMII_TXID
    can have delay in PHY.
    
    So disable the delay only for RGMII mode and enable for other modes.
    Also treat the default case as disabled delays.
    
    Fixes: cd28d1d6e52e: ("net: phy: at803x: Disable phy delay for RGMII mode")

Looking at the git history, it seems like it also took two attempts to
get it working correctly, but the time between the two patches was
much shorted for the atheros PHY.

You will find DT patches converting rgmii to rgmii-id started soon
afterwards.

> I'm generally skeptical about the idea of being able to fix all DTBs,
> some of the problems with that being:
> 
> - There is no way to identify which of of the 2019 dts files in the
>   kernel actually have this particular phy, because it does not
>   have a device node in the dt. Looking only at files that set
>   phy-mode="rgmii" limits it to 235 files, but that is still more than
>   anyone can test.

You can narrow it down a bit. The rtl8211e was added
2014-06-10. Anything older than that, is unlikely to be a problem.
And you can ignore marvell, broadcom, etc boards. They are unlikely to
use a realtek PHY.

But i agree, we cannot test them all. We probably need to look at what
boards we know are broken, and get siblings tested.

> - if there was a way to automate identifying the dts files that
>   need to be modified, we should also be able to do it at runtime

We can get a hint, that there might be a problem, but we can get false
positives. These DT blobs are broken because they rely on strapping
resisters to put the PHY into the correct RGMII mode. We can read
these strapping resistors and compare them against what the software
is asking for. If they differ, it could be the DT blob is buggy. But
there are cases where the DT blob is correct, the strapping is wrong,
eg Pine64 Plus. It is doing everything correctly in DT.

> I agree this makes the problem harder, but I have still hope that
> we can come up with a code solution that can deal with this
> one board that needs to have the correct settings applied as well
> as the others on which we have traditionally ignored them.
> 
> As I understand it so far, the reason this board needs a different
> setting is that the strapping pins are wired incorrectly, while all
> other boards set them right and work correctly by default. I would
> much prefer a way to identify this behavior in dts and have the phy
> driver just warn when it finds a mismatch between the internal
> delay setting in DT and the strapping pins but keep using the
> setting from the strapping pins when there is a conflict.

So what you are suggesting is that the pine board, and any other board
which comes along in the future using this PHY which really wants
RGMII, needs a boolean DT property:

"realtek,IRealyDoWantRGMII_IAmNotBroken"

in the PHY node?

And if it is missing, we ignore when the MAC asks for RGMII and
actually do RGMII_ID?

We might also need to talk to the FreeBSD folks.

https://reviews.freebsd.org/D13591

Do we need to ask them to be bug compatible to Linux? Are the same DT
file being used?

That still leaves ACPI systems. Do we want to stuff this DT property
into an ACPI table? That seems to go against what ACPI people say
saying, ACPI is not DT with an extra wrapper around it.

   Andrew

  reply index

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-17 14:20 Ard Biesheuvel
2020-10-17 14:44 ` Andrew Lunn
2020-10-17 14:46   ` Ard Biesheuvel
2020-10-17 15:11     ` Andrew Lunn
2020-10-17 15:18       ` Ard Biesheuvel
2020-10-17 16:14         ` Ilias Apalodimas
2020-10-17 16:17           ` Ard Biesheuvel
2020-10-17 16:21             ` Ilias Apalodimas
2020-10-17 18:04             ` Andrew Lunn
2020-10-17 18:11               ` Ard Biesheuvel
2020-10-17 18:17                 ` Ard Biesheuvel
2020-10-17 18:27                 ` Andrew Lunn
2020-10-17 18:55                   ` Ard Biesheuvel
2020-10-17 19:49                     ` Andrew Lunn
2020-10-17 22:19                       ` Ard Biesheuvel
2020-10-17 23:02                         ` Andrew Lunn
2020-10-18 10:35                           ` Ard Biesheuvel
2020-10-18 10:56                             ` Ard Biesheuvel
2020-10-18 15:45                               ` Andrew Lunn
2020-10-25 14:16                                 ` Ard Biesheuvel
2020-10-25 14:28                                   ` Andrew Lunn
2020-10-25 14:34                                     ` Ard Biesheuvel
2020-10-25 14:42                                       ` Andrew Lunn
2020-10-29 14:21                                         ` Ilias Apalodimas
2020-10-29 14:39                                           ` Andrew Lunn
2020-10-29 14:42                                             ` Ard Biesheuvel
2020-10-29 14:50                                               ` Andrew Lunn
2020-10-29 14:46                                             ` Ilias Apalodimas
2020-11-05 17:31                                               ` Jernej Škrabec
2020-11-13 13:50                                                 ` Arnd Bergmann
2020-11-13 14:44                                                   ` Andrew Lunn
2020-11-13 15:33                                                     ` Arnd Bergmann
2020-11-13 16:56                                                       ` Andrew Lunn [this message]
2020-11-13 21:26                                                         ` Arnd Bergmann
2020-11-13 22:43                                                           ` Andrew Lunn
2020-11-13 22:49                                                             ` Ard Biesheuvel
2020-11-14  0:40                                                               ` Andrew Lunn
2020-11-14 10:09                                                                 ` Ard Biesheuvel
2020-10-18 15:38                             ` Andrew Lunn
2020-10-18 14:20                         ` Masami Hiramatsu
2020-10-17 18:01           ` Andrew Lunn

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