From: Steen Hegelund <steen.hegelund@microchip.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: Kishon Vijay Abraham I <kishon@ti.com>,
Vinod Koul <vkoul@kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
Lars Povlsen <lars.povlsen@microchip.com>,
Bjarni Jonasson <bjarni.jonasson@microchip.com>,
Microchip UNG Driver List <UNGLinuxDriver@microchip.com>,
<netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v9 3/4] phy: Add Sparx5 ethernet serdes PHY driver
Date: Thu, 10 Dec 2020 15:59:35 +0100 [thread overview]
Message-ID: <20201210145935.see4n6csnomsl2rx@mchp-dev-shegelun> (raw)
In-Reply-To: <20201210141610.GG2638572@lunn.ch>
On 10.12.2020 15:16, Andrew Lunn wrote:
>EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
>> > So why are returning link up information?
>>
>> Yes that was a bit of a hijacking of the function. I will remove that.
>> I also removed the dependency on this behaviour in the client driver in the
>> meantime.
>>
>> I think a status function on the generic phy would be useful, but I will
>> take that as separate issue.
>
>In this context of an Ethernet SERDES, do you actually need it? You
>would normally look at the PCS link status to determine if the link is
>up. But it is useful debug information. If the PCS is down, but the
>PHY indicates up, you can guess you have a protocol misconfiguration.
Yes - you are probably right about that. I have been exposing this via
a procfs interface during the development phase, and it was really
useful to have, to track down the origin of the problem in certain situations.
But on a system level, the PCS link would have the final say anyway.
>
>What exactly does link at this level mean? And thinking of the wider
>uses of the PHY subsystem, what would link mean at this level for
>SATA, PCIe, USB? Don't these all have some protocol level above
>similar to Ethernet PCS which is the real determiner of link?
Yes - I think this is really only a debug feature. No need to force
this on the other PHY categories.
>
> Andrew
Thanks for your comments, Andrew.
BR
Steen
---------------------------------------
Steen Hegelund
steen.hegelund@microchip.com
next prev parent reply other threads:[~2020-12-10 15:01 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-07 12:13 [PATCH v9 0/4] Adding the Sparx5 Serdes driver Steen Hegelund
2020-12-07 12:13 ` [PATCH v9 1/4] dt-bindings: phy: Add sparx5-serdes bindings Steen Hegelund
2020-12-07 18:24 ` Rob Herring
2020-12-07 12:13 ` [PATCH v9 2/4] phy: Add ethernet serdes configuration option Steen Hegelund
2020-12-07 12:13 ` [PATCH v9 3/4] phy: Add Sparx5 ethernet serdes PHY driver Steen Hegelund
2020-12-10 2:11 ` Andrew Lunn
2020-12-10 12:57 ` Steen Hegelund
2020-12-10 14:16 ` Andrew Lunn
2020-12-10 14:59 ` Steen Hegelund [this message]
2020-12-07 12:13 ` [PATCH v9 4/4] arm64: dts: sparx5: Add Sparx5 serdes driver node Steen Hegelund
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