From: Steen Hegelund <steen.hegelund@microchip.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Vinod Koul <vkoul@kernel.org>, "Rob Herring" <robh+dt@kernel.org>,
Device Tree List <devicetree@vger.kernel.org>
Cc: Steen Hegelund <steen.hegelund@microchip.com>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
Lars Povlsen <lars.povlsen@microchip.com>,
Bjarni Jonasson <bjarni.jonasson@microchip.com>,
Microchip UNG Driver List <UNGLinuxDriver@microchip.com>,
<netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Rob Herring <robh@kernel.org>, Andrew Lunn <andrew@lunn.ch>
Subject: [PATCH v15 1/4] dt-bindings: phy: Add sparx5-serdes bindings
Date: Thu, 18 Feb 2021 17:14:48 +0100 [thread overview]
Message-ID: <20210218161451.3489955-2-steen.hegelund@microchip.com> (raw)
In-Reply-To: <20210218161451.3489955-1-steen.hegelund@microchip.com>
Document the Sparx5 ethernet serdes phy driver bindings.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
.../bindings/phy/microchip,sparx5-serdes.yaml | 100 ++++++++++++++++++
1 file changed, 100 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
diff --git a/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml b/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
new file mode 100644
index 000000000000..bdbdb3bbddbe
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Sparx5 Serdes controller
+
+maintainers:
+ - Steen Hegelund <steen.hegelund@microchip.com>
+
+description: |
+ The Sparx5 SERDES interfaces share the same basic functionality, but
+ support different operating modes and line rates.
+
+ The following list lists the SERDES features:
+
+ * RX Adaptive Decision Feedback Equalizer (DFE)
+ * Programmable continuous time linear equalizer (CTLE)
+ * Rx variable gain control
+ * Rx built-in fault detector (loss-of-lock/loss-of-signal)
+ * Adjustable tx de-emphasis (FFE)
+ * Tx output amplitude control
+ * Supports rx eye monitor
+ * Multiple loopback modes
+ * Prbs generator and checker
+ * Polarity inversion control
+
+ SERDES6G:
+
+ The SERDES6G is a high-speed SERDES interface, which can operate at
+ the following data rates:
+
+ * 100 Mbps (100BASE-FX)
+ * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
+ * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
+ * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
+
+ SERDES10G
+
+ The SERDES10G is a high-speed SERDES interface, which can operate at
+ the following data rates:
+
+ * 100 Mbps (100BASE-FX)
+ * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
+ * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
+ * 5 Gbps (QSGMII/USGMII)
+ * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
+ * 10 Gbps (10G-USGMII)
+ * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
+
+ SERDES25G
+
+ The SERDES25G is a high-speed SERDES interface, which can operate at
+ the following data rates:
+
+ * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
+ * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
+ * 5 Gbps (QSGMII/USGMII)
+ * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
+ * 10 Gbps (10G-USGMII)
+ * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
+ * 25.78125 Gbps (25GBASE-KR/25GBASE-CR/25GBASE-SR/25GBASE-LR/25GBASE-ER)
+
+properties:
+ $nodename:
+ pattern: "^serdes@[0-9a-f]+$"
+
+ compatible:
+ const: microchip,sparx5-serdes
+
+ reg:
+ minItems: 1
+
+ '#phy-cells':
+ const: 1
+ description: |
+ - The main serdes input port
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - '#phy-cells'
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ serdes: serdes@10808000 {
+ compatible = "microchip,sparx5-serdes";
+ #phy-cells = <1>;
+ clocks = <&sys_clk>;
+ reg = <0x10808000 0x5d0000>;
+ };
+
+...
--
2.30.0
next prev parent reply other threads:[~2021-02-18 17:44 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-18 16:14 [PATCH v15 0/4] Adding the Sparx5 Serdes driver Steen Hegelund
2021-02-18 16:14 ` Steen Hegelund [this message]
2021-02-18 16:14 ` [PATCH v15 2/4] phy: Add media type and speed serdes configuration interfaces Steen Hegelund
2021-02-21 5:59 ` Leon Romanovsky
2021-02-22 8:00 ` Steen Hegelund
2021-02-23 12:22 ` Kishon Vijay Abraham I
2021-02-23 13:53 ` Leon Romanovsky
2021-03-16 13:14 ` Kishon Vijay Abraham I
2021-02-18 16:14 ` [PATCH v15 3/4] phy: Add Sparx5 ethernet serdes PHY driver Steen Hegelund
2021-02-18 16:14 ` [PATCH v15 4/4] arm64: dts: sparx5: Add Sparx5 serdes driver node Steen Hegelund
2021-02-18 21:23 ` [PATCH v15 0/4] Adding the Sparx5 Serdes driver David Miller
2021-03-15 15:04 ` Steen Hegelund
2021-03-15 17:26 ` Jakub Kicinski
2021-03-16 8:04 ` Steen Hegelund
2021-03-16 4:53 ` Vinod Koul
2021-03-16 8:05 ` Steen Hegelund
2021-03-17 6:43 ` Vinod Koul
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