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From: Saeed Mahameed <saeed@kernel.org>
To: "David S. Miller" <davem@davemloft.net>,
	Jakub Kicinski <kuba@kernel.org>
Cc: netdev@vger.kernel.org, Tariq Toukan <tariqt@nvidia.com>,
	Daniel Jurgens <danielj@mellanox.com>,
	Parav Pandit <parav@nvidia.com>,
	Saeed Mahameed <saeedm@nvidia.com>
Subject: [net 7/9] net/mlx5: Don't request more than supported EQs
Date: Wed, 31 Mar 2021 13:14:22 -0700	[thread overview]
Message-ID: <20210331201424.331095-8-saeed@kernel.org> (raw)
In-Reply-To: <20210331201424.331095-1-saeed@kernel.org>

From: Daniel Jurgens <danielj@mellanox.com>

Calculating the number of compeltion EQs based on the number of
available IRQ vectors doesn't work now that all async EQs share one IRQ.
Thus the max number of EQs can be exceeded on systems with more than
approximately 256 CPUs. Take this into account when calculating the
number of available completion EQs.

Fixes: 81bfa206032a ("net/mlx5: Use a single IRQ for all async EQs")
Signed-off-by: Daniel Jurgens <danielj@mellanox.com>
Reviewed-by: Parav Pandit <parav@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
 drivers/net/ethernet/mellanox/mlx5/core/eq.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/ethernet/mellanox/mlx5/core/eq.c
index 174dfbc996c6..1fa9c18563da 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c
@@ -931,13 +931,24 @@ void mlx5_core_eq_free_irqs(struct mlx5_core_dev *dev)
 	mutex_unlock(&table->lock);
 }
 
+#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
+#define MLX5_MAX_ASYNC_EQS 4
+#else
+#define MLX5_MAX_ASYNC_EQS 3
+#endif
+
 int mlx5_eq_table_create(struct mlx5_core_dev *dev)
 {
 	struct mlx5_eq_table *eq_table = dev->priv.eq_table;
+	int num_eqs = MLX5_CAP_GEN(dev, max_num_eqs) ?
+		      MLX5_CAP_GEN(dev, max_num_eqs) :
+		      1 << MLX5_CAP_GEN(dev, log_max_eq);
 	int err;
 
 	eq_table->num_comp_eqs =
-		mlx5_irq_get_num_comp(eq_table->irq_table);
+		min_t(int,
+		      mlx5_irq_get_num_comp(eq_table->irq_table),
+		      num_eqs - MLX5_MAX_ASYNC_EQS);
 
 	err = create_async_eqs(dev);
 	if (err) {
-- 
2.30.2


  parent reply	other threads:[~2021-03-31 20:17 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-31 20:14 [pull request][net 0/9] mlx5 fixes 2021-03-31 Saeed Mahameed
2021-03-31 20:14 ` [net 1/9] net/mlx5e: Fix mapping of ct_label zero Saeed Mahameed
2021-03-31 22:00   ` patchwork-bot+netdevbpf
2021-03-31 20:14 ` [net 2/9] net/mlx5: Delete auxiliary bus driver eth-rep first Saeed Mahameed
2021-03-31 20:14 ` [net 3/9] net/mlx5e: Fix ethtool indication of connector type Saeed Mahameed
2021-03-31 20:14 ` [net 4/9] net/mlx5: E-switch, Create vport miss group only if src rewrite is supported Saeed Mahameed
2021-03-31 20:14 ` [net 5/9] net/mlx5e: kTLS, Fix TX counters atomicity Saeed Mahameed
2021-03-31 20:14 ` [net 6/9] net/mlx5e: kTLS, Fix RX " Saeed Mahameed
2021-03-31 20:14 ` Saeed Mahameed [this message]
2021-03-31 20:14 ` [net 8/9] net/mlx5e: Consider geneve_opts for encap contexts Saeed Mahameed
2021-03-31 20:14 ` [net 9/9] net/mlx5e: Guarantee room for XSK wakeup NOP on async ICOSQ Saeed Mahameed

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