From: "Marek Behún" <kabel@kernel.org>
To: netdev@vger.kernel.org, Russell King <rmk+kernel@armlinux.org.uk>,
Andrew Lunn <andrew@lunn.ch>
Cc: "David S . Miller" <davem@davemloft.net>,
kuba@kernel.org, "Marek Behún" <kabel@kernel.org>
Subject: [PATCH net-next v4 10/16] net: phy: marvell10g: support other MACTYPEs
Date: Wed, 7 Apr 2021 22:22:48 +0200 [thread overview]
Message-ID: <20210407202254.29417-11-kabel@kernel.org> (raw)
In-Reply-To: <20210407202254.29417-1-kabel@kernel.org>
Currently the only "changing" MACTYPE we support is when the PHY changes
between
10gbase-r / 5gbase-r / 2500base-x / sgmii
Add support for
usxgmii
xaui / 5gbase-r / 2500base-x / sgmii
rxaui / 5gbase-r / 2500base-x / sgmii
and also
5gbase-r / 2500base-x / sgmii
for 88E2110.
Signed-off-by: Marek Behún <kabel@kernel.org>
---
drivers/net/phy/marvell10g.c | 90 +++++++++++++++++++++---------------
1 file changed, 54 insertions(+), 36 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 20d3e572c935..2dc1317e601e 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -512,10 +512,18 @@ static int mv2110_init_interface(struct phy_device *phydev, int mactype)
priv->rate_match = false;
- if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) {
+ if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
priv->rate_match = true;
+
+ if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII)
+ priv->const_interface = PHY_INTERFACE_MODE_USXGMII;
+ else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
- }
+ else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER ||
+ mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN)
+ priv->const_interface = PHY_INTERFACE_MODE_NA;
+ else
+ return -EINVAL;
return 0;
}
@@ -531,12 +539,20 @@ static int mv3310_init_interface(struct phy_device *phydev, int mactype)
mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH)
priv->rate_match = true;
- if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
+ if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII)
+ priv->const_interface = PHY_INTERFACE_MODE_USXGMII;
+ else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH ||
+ mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN ||
+ mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER)
priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
- else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH)
+ else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH ||
+ mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI)
priv->const_interface = PHY_INTERFACE_MODE_RXAUI;
- else if (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH)
+ else if (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH ||
+ mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI)
priv->const_interface = PHY_INTERFACE_MODE_XAUI;
+ else
+ return -EINVAL;
return 0;
}
@@ -563,8 +579,10 @@ static int mv3310_config_init(struct phy_device *phydev)
return mactype;
err = chip->init_interface(phydev, mactype);
- if (err)
+ if (err) {
+ phydev_err(phydev, "MACTYPE configuration invalid\n");
return err;
+ }
/* Enable EDPD mode - saving 600mW */
return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
@@ -674,44 +692,44 @@ static void mv3310_update_interface(struct phy_device *phydev)
{
struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
+ if (!phydev->link)
+ return;
+
/* In all of the "* with Rate Matching" modes the PHY interface is fixed
* at 10Gb. The PHY adapts the rate to actual wire speed with help of
* internal 16KB buffer.
+ *
+ * In USXGMII mode the PHY interface mode is also fixed.
*/
- if (priv->rate_match) {
+ if (priv->rate_match ||
+ priv->const_interface == PHY_INTERFACE_MODE_USXGMII) {
phydev->interface = priv->const_interface;
return;
}
- if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
- phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||
- phydev->interface == PHY_INTERFACE_MODE_5GBASER ||
- phydev->interface == PHY_INTERFACE_MODE_10GBASER) &&
- phydev->link) {
- /* The PHY automatically switches its serdes interface (and
- * active PHYXS instance) between Cisco SGMII, 10GBase-R and
- * 2500BaseX modes according to the speed. Florian suggests
- * setting phydev->interface to communicate this to the MAC.
- * Only do this if we are already in one of the above modes.
- */
- switch (phydev->speed) {
- case SPEED_10000:
- phydev->interface = PHY_INTERFACE_MODE_10GBASER;
- break;
- case SPEED_5000:
- phydev->interface = PHY_INTERFACE_MODE_5GBASER;
- break;
- case SPEED_2500:
- phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
- break;
- case SPEED_1000:
- case SPEED_100:
- case SPEED_10:
- phydev->interface = PHY_INTERFACE_MODE_SGMII;
- break;
- default:
- break;
- }
+ /* The PHY automatically switches its serdes interface (and active PHYXS
+ * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R /
+ * xaui / rxaui modes according to the speed.
+ * Florian suggests setting phydev->interface to communicate this to the
+ * MAC. Only do this if we are already in one of the above modes.
+ */
+ switch (phydev->speed) {
+ case SPEED_10000:
+ phydev->interface = priv->const_interface;
+ break;
+ case SPEED_5000:
+ phydev->interface = PHY_INTERFACE_MODE_5GBASER;
+ break;
+ case SPEED_2500:
+ phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
+ break;
+ case SPEED_1000:
+ case SPEED_100:
+ case SPEED_10:
+ phydev->interface = PHY_INTERFACE_MODE_SGMII;
+ break;
+ default:
+ break;
}
}
--
2.26.2
next prev parent reply other threads:[~2021-04-07 20:25 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-07 20:22 [PATCH net-next v4 00/16] net: phy: marvell10g updates Marek Behún
2021-04-07 20:22 ` [PATCH net-next v4 01/16] net: phy: marvell10g: rename register Marek Behún
2021-04-07 20:22 ` [PATCH net-next v4 02/16] net: phy: marvell10g: fix typo Marek Behún
2021-04-07 20:22 ` [PATCH net-next v4 03/16] net: phy: marvell10g: allow 5gbase-r and usxgmii Marek Behún
2021-04-07 20:22 ` [PATCH net-next v4 04/16] net: phy: marvell10g: indicate 88X33x0 only port control registers Marek Behún
2021-04-07 20:22 ` [PATCH net-next v4 05/16] net: phy: marvell10g: add all MACTYPE definitions for 88X33x0 Marek Behún
2021-04-07 20:22 ` [PATCH net-next v4 06/16] net: phy: marvell10g: add MACTYPE definitions for 88E21xx Marek Behún
2021-04-07 20:22 ` [PATCH net-next v4 07/16] net: phy: marvell10g: support all rate matching modes Marek Behún
2021-04-07 23:03 ` Andrew Lunn
2021-04-07 20:22 ` [PATCH net-next v4 08/16] net: phy: marvell10g: check for correct supported interface mode Marek Behún
2021-04-07 23:05 ` Andrew Lunn
2021-04-07 20:22 ` [PATCH net-next v4 09/16] net: phy: marvell10g: store temperature read method in chip strucutre Marek Behún
2021-04-07 20:22 ` Marek Behún [this message]
2021-04-07 20:22 ` [PATCH net-next v4 11/16] net: phy: marvell10g: add separate structure for 88X3340 Marek Behún
2021-04-07 23:09 ` Andrew Lunn
2021-07-10 16:12 ` Matteo Croce
2021-07-11 13:09 ` Marek Behún
2021-04-07 20:22 ` [PATCH net-next v4 12/16] net: phy: marvell10g: fix driver name for mv88e2110 Marek Behún
2021-04-07 20:22 ` [PATCH net-next v4 13/16] net: phy: add constants for 2.5G and 5G speed in PCS speed register Marek Behún
2021-04-07 20:22 ` [PATCH net-next v4 14/16] net: phy: marvell10g: differentiate 88E2110 vs 88E2111 Marek Behún
2021-04-07 23:10 ` Andrew Lunn
2021-04-07 20:22 ` [PATCH net-next v4 15/16] net: phy: marvell10g: change module description Marek Behún
2021-04-07 20:22 ` [PATCH net-next v4 16/16] MAINTAINERS: add myself as maintainer of marvell10g driver Marek Behún
2021-04-08 20:20 ` [PATCH net-next v4 00/16] net: phy: marvell10g updates patchwork-bot+netdevbpf
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