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Miller" , Jakub Kicinski , Russell King , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list , "open list:OCELOT ETHERNET SWITCH DRIVER" Subject: Re: [RFC PATCH vN net-next 2/2] net: mscc: ocelot: add support for VSC75XX SPI control Thread-Topic: [RFC PATCH vN net-next 2/2] net: mscc: ocelot: add support for VSC75XX SPI control Thread-Index: AQHXQKP/w6NmRV8LhkOQoP6VPcP45arTQY4AgAAH3AA= Date: Tue, 4 May 2021 12:59:43 +0000 Message-ID: <20210504125942.nx5b6j2cy34qyyhm@skbuf> References: <20210504051130.1207550-1-colin.foster@in-advantage.com> <20210504051130.1207550-2-colin.foster@in-advantage.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: lunn.ch; dkim=none (message not signed) header.d=none;lunn.ch; dmarc=none action=none header.from=nxp.com; x-originating-ip: [86.127.41.210] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: f2382902-b8a8-42e7-2859-08d90efc7cba x-ms-traffictypediagnostic: VI1PR0402MB3406: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; 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charset="us-ascii" Content-ID: <8C3A98F4575F44488AB4145C25648932@eurprd04.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5136.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: f2382902-b8a8-42e7-2859-08d90efc7cba X-MS-Exchange-CrossTenant-originalarrivaltime: 04 May 2021 12:59:43.5568 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: oSz41ET9OFRT/mfKL82yz2ezTJlB9b4epNG8XRy8CkgZ5vWbuolnlplOmWI2aazlRwIcl1+G5cbPOLB9OVIoAQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0402MB3406 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Tue, May 04, 2021 at 02:31:34PM +0200, Andrew Lunn wrote: > On Mon, May 03, 2021 at 10:11:27PM -0700, Colin Foster wrote: > > Add support for control for VSC75XX chips over SPI control. Starting wi= th the > > VSC9959 code, this will utilize a spi bus instead of PCIe or memory-map= ped IO to > > control the chip. >=20 > Hi Colin >=20 > Please fix your subject line for the next version. vN should of been > v1. The number is important so we can tell revisions apart. Yes, it was my indication to use --subject-prefix=3D"[PATCH vN net-next]", I was expecting Colin to replace N with 1, 2, 3 etc but I didn't make that clear enough :) > >=20 > > Signed-off-by: Colin Foster > > --- > > arch/arm/boot/dts/rpi-vsc7512-spi-overlay.dts | 124 ++ > > drivers/net/dsa/ocelot/Kconfig | 11 + > > drivers/net/dsa/ocelot/Makefile | 5 + > > drivers/net/dsa/ocelot/felix_vsc7512_spi.c | 1214 +++++++++++++++++ > > include/soc/mscc/ocelot.h | 15 + >=20 > Please split this patch up. The DT overlay will probably be merged via > ARM SOC, not netdev. You also need to document the device tree > binding, as a separate patch. >=20 > > + fragment@3 { > > + target =3D <&spi0>; > > + __overlay__ { > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + cs-gpios =3D <&gpio 8 1>; > > + status =3D "okay"; > > + > > + vsc7512: vsc7512@0{ > > + compatible =3D "mscc,vsc7512"; > > + spi-max-frequency =3D <250000>; > > + reg =3D <0>; > > + > > + ports { > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + > > + port@0 { > > + reg =3D <0>; > > + ethernet =3D <ðernet>; > > + phy-mode =3D "internal"; Additionally, being a completely off-chip switch, are you sure that the phy-mode is "internal"? > > + fixed-link { > > + speed =3D <1000>; > > + full-duplex; > > + }; > > + }; > > + > > + port@1 { > > + reg =3D <1>; > > + label =3D "swp1"; > > + status =3D "disabled"; > > + }; > > + > > + port@2 { > > + reg =3D <2>; > > + label =3D "swp2"; > > + status =3D "disabled"; > > + }; > > +static void vsc7512_phylink_validate(struct ocelot *ocelot, int port, > > + unsigned long *supported, > > + struct phylink_link_state *state) > > +{ > > + struct ocelot_port *ocelot_port =3D ocelot->ports[port]; > > + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) =3D { > > + 0, > > + }; >=20 > This function seems out of place. Why would SPI access change what the > ports are capable of doing? Please split this up into more > patches. Keep the focus of this patch as being adding SPI support. What is going on is that this is just the way in which the drivers are structured. Colin is not really "adding SPI support" to any of the existing DSA switches that are supported (VSC9953, VSC9959) as much as "adding support for a new switch which happens to be controlled over SPI" (VSC7512). The layering is as follows: - drivers/net/dsa/ocelot/felix_vsc7512_spi.c: deals with the most hardware specific SoC support. The regmap is defined here, so are the port capabilities. - drivers/net/dsa/ocelot/felix.c: common integration with DSA - drivers/net/ethernet/mscc/ocelot*.c: the SoC-independent hardware support. I'm not actually sure that splitting the port PHY mode support in a separate patch is possible while keeping functional intermediate results. But I do agree about the rest, splitting the device tree changes, etc.=