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From: Arnd Bergmann <arnd@kernel.org>
To: "David S. Miller" <davem@davemloft.net>,
	Jakub Kicinski <kuba@kernel.org>,
	Lars Povlsen <lars.povlsen@microchip.com>,
	Steen Hegelund <Steen.Hegelund@microchip.com>,
	UNGLinuxDriver@microchip.com,
	Bjarni Jonasson <bjarni.jonasson@microchip.com>
Cc: Arnd Bergmann <arnd@arndb.de>,
	netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH] net: sparx5: fix bitmask check
Date: Mon,  2 Aug 2021 16:54:37 +0200	[thread overview]
Message-ID: <20210802145449.1154565-1-arnd@kernel.org> (raw)

From: Arnd Bergmann <arnd@arndb.de>

Older compilers such as gcc-5.5 produce a warning in this driver
when ifh_encode_bitfield() is not getting inlined:

drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c: In function 'ifh_encode_bitfield':
include/linux/compiler_types.h:333:38: error: call to '__compiletime_assert_545' declared with attribute error: Unsupported width, must be <= 40
drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c:28:2: note: in expansion of macro 'compiletime_assert'
  compiletime_assert(width <= 40, "Unsupported width, must be <= 40");
  ^

Mark the function as __always_inline to make the check work correctly
on all compilers. To make this also work on 32-bit architectures, change
the GENMASK() to GENMASK_ULL().

Fixes: f3cad2611a77 ("net: sparx5: add hostmode with phylink support")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c
index 9d485a9d1f1f..6f362f6708c6 100644
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c
@@ -13,14 +13,15 @@
  */
 #define VSTAX 73
 
-static void ifh_encode_bitfield(void *ifh, u64 value, u32 pos, u32 width)
+static __always_inline void ifh_encode_bitfield(void *ifh, u64 value,
+						u32 pos, u32 width)
 {
 	u8 *ifh_hdr = ifh;
 	/* Calculate the Start IFH byte position of this IFH bit position */
 	u32 byte = (35 - (pos / 8));
 	/* Calculate the Start bit position in the Start IFH byte */
 	u32 bit  = (pos % 8);
-	u64 encode = GENMASK(bit + width - 1, bit) & (value << bit);
+	u64 encode = GENMASK_ULL(bit + width - 1, bit) & (value << bit);
 
 	/* Max width is 5 bytes - 40 bits. In worst case this will
 	 * spread over 6 bytes - 48 bits
-- 
2.29.2


             reply	other threads:[~2021-08-02 14:54 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-02 14:54 Arnd Bergmann [this message]
2021-08-02 15:02 ` [PATCH] net: sparx5: fix bitmask check Jakub Kicinski
2021-08-02 15:21   ` Arnd Bergmann

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