From: Ansuel Smith <ansuelsmth@gmail.com>
To: Andrew Lunn <andrew@lunn.ch>,
Vivien Didelot <vivien.didelot@gmail.com>,
Florian Fainelli <f.fainelli@gmail.com>,
Vladimir Oltean <olteanv@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Russell King <linux@armlinux.org.uk>,
netdev@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Ansuel Smith <ansuelsmth@gmail.com>
Subject: [net-next PATCH v3 13/13] drivers: net: dsa: qca8k: set internal delay also for sgmii
Date: Sun, 10 Oct 2021 03:56:03 +0200 [thread overview]
Message-ID: <20211010015603.24483-14-ansuelsmth@gmail.com> (raw)
In-Reply-To: <20211010015603.24483-1-ansuelsmth@gmail.com>
QCA original code report port instability and sa that SGMII also require
to set internal delay. Generalize the rgmii delay function and apply the
advised value if they are not defined in DT.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/net/dsa/qca8k.c | 102 +++++++++++++++++++++++++---------------
drivers/net/dsa/qca8k.h | 2 +
2 files changed, 67 insertions(+), 37 deletions(-)
diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index 7c68c272ce3a..21776826bf2e 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -1164,13 +1164,67 @@ qca8k_setup(struct dsa_switch *ds)
return 0;
}
+static void
+qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, struct dsa_port *dp,
+ u32 reg, const struct phylink_link_state *state)
+{
+ u32 delay, val = 0;
+ int ret;
+
+ if (state->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ state->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
+ state->interface == PHY_INTERFACE_MODE_SGMII) {
+ if (of_property_read_u32(dp->dn, "tx-internal-delay-ps", &delay))
+ delay = 1;
+ else
+ /* Switch regs accept value in ns, convert ps to ns */
+ delay = delay / 1000;
+
+ if (delay > QCA8K_MAX_DELAY) {
+ dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
+ delay = 3;
+ }
+
+ val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |
+ QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;
+ }
+
+ if (state->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+ state->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
+ state->interface == PHY_INTERFACE_MODE_SGMII) {
+ if (of_property_read_u32(dp->dn, "rx-internal-delay-ps", &delay))
+ delay = 2;
+ else
+ /* Switch regs accept value in ns, convert ps to ns */
+ delay = delay / 1000;
+
+ if (delay > QCA8K_MAX_DELAY) {
+ dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
+ delay = 3;
+ }
+
+ val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |
+ QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;
+ }
+
+ /* Set RGMII delay based on the selected values */
+ ret = qca8k_rmw(priv, reg,
+ QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK |
+ QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK |
+ QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK |
+ QCA8K_PORT_PAD_RGMII_RX_DELAY_EN,
+ val);
+ if (ret)
+ dev_err(priv->dev, "Failed to set internal delay for CPU port %d", dp->index);
+}
+
static void
qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
const struct phylink_link_state *state)
{
struct qca8k_priv *priv = ds->priv;
struct dsa_port *dp;
- u32 reg, val, delay;
+ u32 reg, val;
int ret;
switch (port) {
@@ -1222,44 +1276,11 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
dp = dsa_to_port(ds, port);
- val = QCA8K_PORT_PAD_RGMII_EN;
-
- if (state->interface == PHY_INTERFACE_MODE_RGMII_ID ||
- state->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
- if (of_property_read_u32(dp->dn, "tx-internal-delay-ps", &delay))
- delay = 1;
- else
- /* Switch regs accept value in ns, convert ps to ns */
- delay = delay / 1000;
-
- if (delay > QCA8K_MAX_DELAY) {
- dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
- delay = 3;
- }
-
- val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |
- QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;
- }
- if (state->interface == PHY_INTERFACE_MODE_RGMII_ID ||
- state->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
- if (of_property_read_u32(dp->dn, "rx-internal-delay-ps", &delay))
- delay = 2;
- else
- /* Switch regs accept value in ns, convert ps to ns */
- delay = delay / 1000;
-
- if (delay > QCA8K_MAX_DELAY) {
- dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
- delay = 3;
- }
-
- val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |
- QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;
- }
+ qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
- /* Set RGMII delay based on the selected values */
- qca8k_write(priv, reg, val);
+ /* Configure rgmii delay from dp or taking advised values */
+ qca8k_mac_config_setup_internal_delay(priv, dp, reg, state);
/* QCA8337 requires to set rgmii rx delay for all ports.
* This is enabled through PORT5_PAD_CTRL for all ports,
@@ -1341,6 +1362,13 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
val);
+
+ /* From original code is reported port instability as SGMII also
+ * require delay set. Apply advised values here or take them from DT.
+ */
+ if (state->interface == PHY_INTERFACE_MODE_SGMII)
+ qca8k_mac_config_setup_internal_delay(priv, dp, reg, state);
+
break;
default:
dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index c032db5e0d41..92867001cc34 100644
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -39,7 +39,9 @@
#define QCA8K_REG_PORT5_PAD_CTRL 0x008
#define QCA8K_REG_PORT6_PAD_CTRL 0x00c
#define QCA8K_PORT_PAD_RGMII_EN BIT(26)
+#define QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK GENMASK(23, 22)
#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) ((x) << 22)
+#define QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK GENMASK(21, 20)
#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) ((x) << 20)
#define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN BIT(25)
#define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24)
--
2.32.0
prev parent reply other threads:[~2021-10-10 1:57 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-10 1:55 [net-next PATCH v3 00/13] Multiple improvement for qca8337 switch Ansuel Smith
2021-10-10 1:55 ` [net-next PATCH v3 01/13] net: dsa: qca8k: add mac_power_sel support Ansuel Smith
2021-10-10 1:55 ` [net-next PATCH v3 02/13] net: dsa: qca8k: add support for sgmii falling edge Ansuel Smith
2021-10-10 6:12 ` kernel test robot
2021-10-10 1:55 ` [net-next PATCH v3 03/13] dt-bindings: net: dsa: qca8k: Add MAC swap and clock phase properties Ansuel Smith
2021-10-10 1:55 ` [net-next PATCH v3 04/13] drivers: net: dsa: qca8k: add support for cpu port 6 Ansuel Smith
2021-10-10 1:55 ` [net-next PATCH v3 05/13] dt-bindings: net: dsa: qca8k: Document support for CPU " Ansuel Smith
2021-10-10 1:55 ` [net-next PATCH v3 06/13] net: dsa: qca8k: move rgmii delay detection to phylink mac_config Ansuel Smith
2021-10-10 1:55 ` [net-next PATCH v3 07/13] net: dsa: qca8k: add explicit SGMII PLL enable Ansuel Smith
2021-10-10 1:55 ` [net-next PATCH v3 08/13] dt-bindings: net: dsa: qca8k: Document qca,sgmii-enable-pll Ansuel Smith
2021-10-10 1:55 ` [net-next PATCH v3 09/13] drivers: net: dsa: qca8k: add support for pws config reg Ansuel Smith
2021-10-10 1:56 ` [net-next PATCH v3 10/13] dt-bindings: net: dsa: qca8k: document open drain binding Ansuel Smith
2021-10-10 1:56 ` [net-next PATCH v3 11/13] drivers: net: dsa: qca8k: add support for QCA8328 Ansuel Smith
2021-10-10 1:56 ` [net-next PATCH v3 12/13] dt-bindings: net: dsa: qca8k: document support for qca8328 Ansuel Smith
2021-10-10 1:56 ` Ansuel Smith [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211010015603.24483-14-ansuelsmth@gmail.com \
--to=ansuelsmth@gmail.com \
--cc=andrew@lunn.ch \
--cc=davem@davemloft.net \
--cc=devicetree@vger.kernel.org \
--cc=f.fainelli@gmail.com \
--cc=kuba@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux@armlinux.org.uk \
--cc=netdev@vger.kernel.org \
--cc=olteanv@gmail.com \
--cc=robh+dt@kernel.org \
--cc=vivien.didelot@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).