From: David Thompson <davthompson@nvidia.com>
To: <davem@davemloft.net>, <kuba@kernel.org>, <pabeni@redhat.com>,
<edumazet@google.com>
Cc: <netdev@vger.kernel.org>, <limings@nvidia.com>,
<cai.huoqing@linux.dev>, David Thompson <davthompson@nvidia.com>,
Asmaa Mnebhi <asmaa@nvidia.com>
Subject: [PATCH net-next v1] mlxbf_gige: remove driver-managed interrupt counts
Date: Mon, 9 May 2022 11:24:26 -0400 [thread overview]
Message-ID: <20220509152426.28800-1-davthompson@nvidia.com> (raw)
The driver currently has three interrupt counters,
which are incremented every time each interrupt handler
executes. These driver-managed counters are not
necessary as the kernel already has logic that manages
interrupt counts and exposes them via /proc/interrupts.
This patch removes the driver-managed counters, and thus
removes them from "ethtool -S" output as well.
Signed-off-by: David Thompson <davthompson@nvidia.com>
Signed-off-by: Asmaa Mnebhi <asmaa@nvidia.com>
---
drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h | 3 ---
.../ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c | 8 +++-----
.../net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_intr.c | 9 ---------
3 files changed, 3 insertions(+), 17 deletions(-)
diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h
index 86826a70f9dd..5fdf9b7179f5 100644
--- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h
+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h
@@ -90,9 +90,6 @@ struct mlxbf_gige {
dma_addr_t rx_cqe_base_dma;
u16 tx_pi;
u16 prev_tx_ci;
- u64 error_intr_count;
- u64 rx_intr_count;
- u64 llu_plu_intr_count;
struct sk_buff *rx_skb[MLXBF_GIGE_MAX_RXQ_SZ];
struct sk_buff *tx_skb[MLXBF_GIGE_MAX_TXQ_SZ];
int error_irq;
diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c
index ceeb7f4c3f6c..41ebef25a930 100644
--- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c
+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c
@@ -24,11 +24,9 @@ static void mlxbf_gige_get_regs(struct net_device *netdev,
regs->version = MLXBF_GIGE_REGS_VERSION;
/* Read entire MMIO register space and store results
- * into the provided buffer. Each 64-bit word is converted
- * to big-endian to make the output more readable.
- *
- * NOTE: by design, a read to an offset without an existing
- * register will be acknowledged and return zero.
+ * into the provided buffer. By design, a read to an
+ * offset without an existing register will be
+ * acknowledged and return zero.
*/
memcpy_fromio(p, priv->base, MLXBF_GIGE_MMIO_REG_SZ);
}
diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_intr.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_intr.c
index c38795be04a2..5b3519f0cc46 100644
--- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_intr.c
+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_intr.c
@@ -17,8 +17,6 @@ static irqreturn_t mlxbf_gige_error_intr(int irq, void *dev_id)
priv = dev_id;
- priv->error_intr_count++;
-
int_status = readq(priv->base + MLXBF_GIGE_INT_STATUS);
if (int_status & MLXBF_GIGE_INT_STATUS_HW_ACCESS_ERROR)
@@ -75,8 +73,6 @@ static irqreturn_t mlxbf_gige_rx_intr(int irq, void *dev_id)
priv = dev_id;
- priv->rx_intr_count++;
-
/* NOTE: GigE silicon automatically disables "packet rx" interrupt by
* setting MLXBF_GIGE_INT_MASK bit0 upon triggering the interrupt
* to the ARM cores. Software needs to re-enable "packet rx"
@@ -90,11 +86,6 @@ static irqreturn_t mlxbf_gige_rx_intr(int irq, void *dev_id)
static irqreturn_t mlxbf_gige_llu_plu_intr(int irq, void *dev_id)
{
- struct mlxbf_gige *priv;
-
- priv = dev_id;
- priv->llu_plu_intr_count++;
-
return IRQ_HANDLED;
}
--
2.30.1
next reply other threads:[~2022-05-09 15:24 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-09 15:24 David Thompson [this message]
2022-05-10 22:24 ` [PATCH net-next v1] mlxbf_gige: remove driver-managed interrupt counts Jakub Kicinski
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