From: Ido Schimmel <idosch@nvidia.com>
To: netdev@vger.kernel.org
Cc: davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com,
edumazet@google.com, petrm@nvidia.com, amcohen@nvidia.com,
mlxsw@nvidia.com, Ido Schimmel <idosch@nvidia.com>
Subject: [PATCH net-next 09/13] mlxsw: reg: Replace MID related fields in SFGC register
Date: Sun, 19 Jun 2022 13:29:17 +0300 [thread overview]
Message-ID: <20220619102921.33158-10-idosch@nvidia.com> (raw)
In-Reply-To: <20220619102921.33158-1-idosch@nvidia.com>
From: Amit Cohen <amcohen@nvidia.com>
SFGC register maps {packet type, bridge type} -> {MID base, table type}.
As preparation for unified bridge model, remove 'mid' field and add
'mid_base' field.
The MID index (index to PGT table which maps MID to local port list and
SMPE index) is a result of 'mid_base' + 'fid_offset'. Using the legacy
bridge model, firmware configures 'mid_base'. However, using the new model,
software is responsible to configure it via SFGC register.
The 'mid_base' is configured per {packet type, bridge type}, for
example, for {Unicast, .1Q}, {Broadcast, .1D}.
Add the field 'mid_base' to SFGC register and increase the length of the
register accordingly.
Remove the field 'mid' as currently it is ignored by the device, its use
is an old leftover.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
---
drivers/net/ethernet/mellanox/mlxsw/port.h | 2 --
drivers/net/ethernet/mellanox/mlxsw/reg.h | 17 +++++++++--------
2 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/mellanox/mlxsw/port.h b/drivers/net/ethernet/mellanox/mlxsw/port.h
index 741fd2989d12..ac4d4ea51597 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/port.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/port.h
@@ -15,8 +15,6 @@
#define MLXSW_PORT_SWID_TYPE_IB 1
#define MLXSW_PORT_SWID_TYPE_ETH 2
-#define MLXSW_PORT_MID 0xd000
-
#define MLXSW_PORT_MAX_IB_PHY_PORTS 36
#define MLXSW_PORT_MAX_IB_PORTS (MLXSW_PORT_MAX_IB_PHY_PORTS + 1)
diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h
index c32c433c2f93..160a724c9a6a 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/reg.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h
@@ -1032,7 +1032,7 @@ static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port,
* to packet types used for flooding.
*/
#define MLXSW_REG_SFGC_ID 0x2011
-#define MLXSW_REG_SFGC_LEN 0x10
+#define MLXSW_REG_SFGC_LEN 0x14
MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN);
@@ -1089,12 +1089,6 @@ MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
*/
MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
-/* reg_sfgc_mid
- * The multicast ID for the swid. Not supported for Spectrum
- * Access: RW
- */
-MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
-
/* reg_sfgc_counter_set_type
* Counter Set Type for flow counters.
* Access: RW
@@ -1107,6 +1101,14 @@ MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
*/
MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
+/* reg_sfgc_mid_base
+ * MID Base.
+ * Access: RW
+ *
+ * Note: Reserved when legacy bridge model is used.
+ */
+MLXSW_ITEM32(reg, sfgc, mid_base, 0x10, 0, 16);
+
static inline void
mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
enum mlxsw_reg_sfgc_bridge_type bridge_type,
@@ -1118,7 +1120,6 @@ mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
mlxsw_reg_sfgc_table_type_set(payload, table_type);
mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
- mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
}
/* SFDF - Switch Filtering DB Flush
--
2.36.1
next prev parent reply other threads:[~2022-06-19 10:30 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-19 10:29 [PATCH net-next 00/13] mlxsw: Unified bridge conversion - part 1/6 Ido Schimmel
2022-06-19 10:29 ` [PATCH net-next 01/13] mlxsw: reg: Add 'flood_rsp' field to SFMR register Ido Schimmel
2022-06-19 10:29 ` [PATCH net-next 02/13] mlxsw: reg: Add ingress RIF related fields " Ido Schimmel
2022-06-19 10:29 ` [PATCH net-next 03/13] mlxsw: reg: Add ingress RIF related fields to SVFA register Ido Schimmel
2022-06-19 10:29 ` [PATCH net-next 04/13] mlxsw: reg: Add Switch Multicast Port to Egress VID Register Ido Schimmel
2022-06-19 10:29 ` [PATCH net-next 05/13] mlxsw: Add SMPE related fields to SMID2 register Ido Schimmel
2022-06-19 10:29 ` [PATCH net-next 06/13] mlxsw: reg: Add SMPE related fields to SFMR register Ido Schimmel
2022-06-19 10:29 ` [PATCH net-next 07/13] mlxsw: reg: Add VID related fields to SFD register Ido Schimmel
2022-06-19 10:29 ` [PATCH net-next 08/13] mlxsw: reg: Add flood related field to SFMR register Ido Schimmel
2022-06-19 10:29 ` Ido Schimmel [this message]
2022-06-19 10:29 ` [PATCH net-next 10/13] mlxsw: reg: Add Router Egress Interface to VID Register Ido Schimmel
2022-06-19 10:29 ` [PATCH net-next 11/13] mlxsw: reg: Add egress FID field to RITR register Ido Schimmel
2022-06-19 10:29 ` [PATCH net-next 12/13] mlxsw: Add support for egress FID classification after decapsulation Ido Schimmel
2022-06-19 10:29 ` [PATCH net-next 13/13] mlxsw: reg: Add support for VLAN RIF as part of RITR register Ido Schimmel
2022-06-20 9:10 ` [PATCH net-next 00/13] mlxsw: Unified bridge conversion - part 1/6 patchwork-bot+netdevbpf
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