Re: [PATCH net-next 00/15] Realtek RTL822x PHY rework to c45 and SerDes interface switching

From: "Marek Behún" <kabel@kernel.org>
To: Heiner Kallweit <hkallweit1@gmail.com>
Cc: netdev@vger.kernel.org, "Andrew Lunn" <andrew@lunn.ch>,
	"David S. Miller" <davem@davemloft.net>,
	"Jakub Kicinski" <kuba@kernel.org>,
	"Paolo Abeni" <pabeni@redhat.com>,
	"Russell King" <rmk+kernel@armlinux.org.uk>,
	"Alexander Couzens" <lynxis@fe80.eu>,
	"Daniel Golle" <daniel@makrotopia.org>,
	"Willy Liu" <willy.liu@realtek.com>,
	"Ioana Ciornei" <ioana.ciornei@nxp.com>,
	"Marek Mojík" <marek.mojik@nic.cz>,
	"Maximilián Maliar" <maximilian.maliar@nic.cz>
Subject: Re: [PATCH net-next 00/15] Realtek RTL822x PHY rework to c45 and SerDes interface switching
Date: Mon, 25 Dec 2023 11:28:31 +0100	[thread overview]
Message-ID: <20231225112831.65e3a942@thinkpad> (raw)
In-Reply-To: <5b9ae8ea-5817-47b0-9d51-0b15098db5cf@gmail.com>

On Sat, 23 Dec 2023 20:09:33 +0100
Heiner Kallweit <hkallweit1@gmail.com> wrote:

> On 20.12.2023 17:25, Marek Behún wrote:
> > On Wed, 20 Dec 2023 17:20:07 +0100
> > Heiner Kallweit <hkallweit1@gmail.com> wrote:
> >   
> >> On 20.12.2023 16:55, Marek Behún wrote:  
> >>> Hi,
> >>>
> >>> this series reworks the realtek PHY driver's support for rtl822x
> >>> 2.5G transceivers:
> >>>
> >>> - First I change the driver so that the high level driver methods
> >>>   only use clause 45 register accesses (the only clause 22 accesses
> >>>   are left when accessing c45 registers indirectly, if the MDIO bus
> >>>   does not support clause 45 accesses).
> >>>   The driver starts using the genphy_c45_* methods.
> >>>
> >>>   At this point the driver is ready to be used on a MDIO bus capable
> >>>   of only clause 45 accesses, but will still work on clause 22 only
> >>>   MDIO bus.
> >>>
> >>> - I then add support for SerDes mode switching between 2500base-x
> >>>   and sgmii, based on autonegotiated copper speed.
> >>>
> >>> All this is done so that we can support another 2.5G copper SFP
> >>> module, which is enabled by the last patch.
> >>>     
> >>
> >> Has been verified that the RTL8125-integrated PHY's still work
> >> properly with this patch set?
> >>  
> > 
> > Hi Heiner,
> > 
> > no, I wanted to send you an email to test this. I do not have the
> > controllers with integrates PHYs.
> > 
> > Can you test this?
> > 
> > Also do you have a controller where the rtlgen driver is used but it
> > only supports 1gbps ? I.e. where the PHY ID is RTL_GENERIC_PHYID
> > (0x001cc800).
> > 
> > I am asking because I am told that it also is clause 45, so the drivers
> > can potentially be merged completely (the rtl822x_ functions can be
> > merged with rtlgen_ functions and everything rewritten to clause 45,
> > and gentphy_c45_ functions can be used).
> >   
> At least on RTL8168h indirect MMD reads return 0 always.
> IIRC this was the reason why the rtlgen functions use the vendor-specific
> registers.

Looking at the code in r8169_phy_config.c, I see function
  rtl8168h_config_eee_phy()
with three paged writes to vendor registers, but the writes do not access
the same registers as the .read_mmd() methods for the PCS_EEE / AN_EEE registers
in realtek.c PHY driver.

It seems for now it would be best to keep the methods for paged
accesses.

Could you test the patchset without the patch that removes the paged
access methods?

The rewrite of the read_mmd / write_mmd methods should not cause
problems. I am told by the realtek contact you gave me that:

  If FE PHY supports EEE, then it will support MMD register and it will
  also support use internal registers to access theses MMD registers.

Marek