From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 810FB5DF18; Wed, 6 Mar 2024 08:51:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709715087; cv=none; b=FrmzarS8VkStDYX3UzF4qR6BaP4R8xw5akSsC+mVEAV8l3HXmoL1tKLicQXRW0pgY/7LaIRjJIIDj427SSDWIIW28YzDbjnzutyjYViKcRTLYO3lS+334IRLbTwG9GW09FHZ6Su/3TB53X99MwnN6C4cihHF2NgHY3Y6P65HLec= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709715087; c=relaxed/simple; bh=1bwISmyy1PxfGsJiZe7IrdJTGba+bmITcKZYdxhr350=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=C4f+8Is+9oLMVCmVfM5fwkUEYvj14Q2OWuLfLEbZzaz1gy1bkW9AQYcCWDjxByrnnD5VTrk9lV1TzL430Wu7BnZ2AMbp35NXXXVwNB8gI/dUWIrRgObtkJGvAGkcGz2FC+dO8moHt7oqLcFGKCJqYq7dpQ9ff9AzKrblClITwhY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=MxQcwssL; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="MxQcwssL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1709715085; x=1741251085; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1bwISmyy1PxfGsJiZe7IrdJTGba+bmITcKZYdxhr350=; b=MxQcwssLSiTzshsUFg9Gja66ecO/ryIcPEeNST/wzGGixyML3rsxajiv WUdRJQhyXdl3r2Y02/ldN+a4NF1xf8IgC6MmgVdJvmH9lTlNeklO2EnbM 2A9IGPIdQRJ6o8yBgyTRTK8BkFzPlR6pBMj784iyI5ql9C0zhLyjzc3J3 pBUKgVwmUcWetGhoYPRJGSXTFylAJtqT60ZDoWISe/IDTTP0i9ZlojV/5 iA7Q8YSh3VXRNOKBopRYqIhJENItXdSnqZ/PBE0LKLRXdJCDYb94va8Hq Gz+mrzLnh7akg0WAET3ZbS/NoCOcHVyqU3yqWGvsEhFT/QOsV4GWGoWTx Q==; X-CSE-ConnectionGUID: dD6mxt9eTkeG+LSdBVuFYA== X-CSE-MsgGUID: 2qrX19q2QK6u1B8+LI46hw== X-IronPort-AV: E=Sophos;i="6.06,207,1705388400"; d="scan'208";a="17265143" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 06 Mar 2024 01:51:24 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 6 Mar 2024 01:51:12 -0700 Received: from CHE-LT-I17164LX.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 6 Mar 2024 01:51:03 -0700 From: Parthiban Veerasooran To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , Parthiban Veerasooran Subject: [PATCH net-next v3 04/12] net: ethernet: oa_tc6: implement software reset Date: Wed, 6 Mar 2024 14:20:09 +0530 Message-ID: <20240306085017.21731-5-Parthiban.Veerasooran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240306085017.21731-1-Parthiban.Veerasooran@microchip.com> References: <20240306085017.21731-1-Parthiban.Veerasooran@microchip.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Reset complete bit is set when the MAC-PHY reset completes and ready for configuration. Additionally reset complete bit in the STS0 register has to be written by one upon reset complete to clear the interrupt. Signed-off-by: Parthiban Veerasooran --- drivers/net/ethernet/oa_tc6.c | 53 +++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/net/ethernet/oa_tc6.c b/drivers/net/ethernet/oa_tc6.c index 35e377577ba4..e9ddc4ff7d0d 100644 --- a/drivers/net/ethernet/oa_tc6.c +++ b/drivers/net/ethernet/oa_tc6.c @@ -6,8 +6,18 @@ */ #include +#include #include +/* OPEN Alliance TC6 registers */ +/* Reset Control and Status Register */ +#define OA_TC6_REG_RESET 0x0003 +#define RESET_SWRESET BIT(0) /* Software Reset */ + +/* Status Register #0 */ +#define OA_TC6_REG_STATUS0 0x0008 +#define STATUS0_RESETC BIT(6) /* Reset Complete */ + /* Control command header */ #define OA_TC6_CTRL_HEADER_DATA_NOT_CTRL BIT(31) #define OA_TC6_CTRL_HEADER_WRITE BIT(29) @@ -24,6 +34,8 @@ (OA_TC6_CTRL_MAX_REGISTERS *\ OA_TC6_CTRL_REG_VALUE_SIZE) +\ OA_TC6_CTRL_IGNORED_SIZE) +#define STATUS0_RESETC_POLL_DELAY 5 +#define STATUS0_RESETC_POLL_TIMEOUT 100 /* Internal structure for MAC-PHY drivers */ struct oa_tc6 { @@ -279,6 +291,39 @@ int oa_tc6_write_register(struct oa_tc6 *tc6, u32 address, u32 value) } EXPORT_SYMBOL_GPL(oa_tc6_write_register); +static int oa_tc6_read_sw_reset_status(struct oa_tc6 *tc6) +{ + u32 regval; + int ret; + + ret = oa_tc6_read_register(tc6, OA_TC6_REG_STATUS0, ®val); + if (ret) + return 0; + + return regval; +} + +static int oa_tc6_sw_reset_macphy(struct oa_tc6 *tc6) +{ + u32 regval = RESET_SWRESET; + int ret; + + ret = oa_tc6_write_register(tc6, OA_TC6_REG_RESET, regval); + if (ret) + return ret; + + /* Poll for soft reset complete for every 5us until 100us timeout */ + ret = readx_poll_timeout(oa_tc6_read_sw_reset_status, tc6, regval, + regval & STATUS0_RESETC, + STATUS0_RESETC_POLL_DELAY, + STATUS0_RESETC_POLL_TIMEOUT); + if (ret) + return -ENODEV; + + /* Clear the reset complete status */ + return oa_tc6_write_register(tc6, OA_TC6_REG_STATUS0, regval); +} + /** * oa_tc6_init - allocates and initializes oa_tc6 structure. * @spi: device with which data will be exchanged. @@ -289,6 +334,7 @@ EXPORT_SYMBOL_GPL(oa_tc6_write_register); struct oa_tc6 *oa_tc6_init(struct spi_device *spi) { struct oa_tc6 *tc6; + int ret; tc6 = devm_kzalloc(&spi->dev, sizeof(*tc6), GFP_KERNEL); if (!tc6) @@ -311,6 +357,13 @@ struct oa_tc6 *oa_tc6_init(struct spi_device *spi) if (!tc6->spi_ctrl_rx_buf) return NULL; + ret = oa_tc6_sw_reset_macphy(tc6); + if (ret) { + dev_err(&tc6->spi->dev, + "MAC-PHY software reset failed: %d\n", ret); + return NULL; + } + return tc6; } EXPORT_SYMBOL_GPL(oa_tc6_init); -- 2.34.1