Re: PHY reset question

From: Marek Vasut <marex@denx.de>
To: Marco Felsch <m.felsch@pengutronix.de>
Cc: Florian Fainelli <f.fainelli@gmail.com>,
	Oleksij Rempel <o.rempel@pengutronix.de>,
	Andrew Lunn <andrew@lunn.ch>,
	netdev@vger.kernel.org, Russell King <linux@armlinux.org.uk>,
	linux-kernel@vger.kernel.org, mkl@pengutronix.de,
	kernel@pengutronix.de, David Jander <david@protonic.nl>
Subject: Re: PHY reset question
Date: Wed, 7 Oct 2020 11:20:40 +0200	[thread overview]
Message-ID: <2b6a1616-beb8-fd12-9932-1e7d1ef04769@denx.de> (raw)
In-Reply-To: <20201007090636.t5rsus3tnkwuekjj@pengutronix.de>

On 10/7/20 11:06 AM, Marco Felsch wrote:
> On 20-10-07 10:23, Marek Vasut wrote:
>> On 10/7/20 10:14 AM, Marco Felsch wrote:
>>> Hi Marek,
>>
>> Hi,
>>
>> [...]
>>
>>> On 20-10-06 14:11, Florian Fainelli wrote:
>>>> On 10/6/2020 1:24 PM, Marek Vasut wrote:
>>>
>>> ...
>>>
>>>>> If this happens on MX6 with FEC, can you please try these two patches?
>>>>>
>>>>> https://patchwork.ozlabs.org/project/netdev/patch/20201006135253.97395-1-marex@denx.de/
>>>>>
>>>>> https://patchwork.ozlabs.org/project/netdev/patch/20201006202029.254212-1-marex@denx.de/
>>>>
>>>> Your patches are not scaling across multiple Ethernet MAC drivers
>>>> unfortunately, so I am not sure this should be even remotely considered a
>>>> viable solution.
>>>
>>> Recently I added clk support for the smcs driver [1] and dropped the
>>> PHY_RST_AFTER_CLK_EN flag for LAN8710/20 devices because I had the same
>>> issues. Hope this will help you too.
>>>
>>> [1] https://www.spinics.net/lists/netdev/msg682080.html
>>
>> I feel this might be starting to go a bit off-topic here,
> 
> You're right, just wanted to provide you a link :)

Can you CC me on the next version of those patches ? I seems the LAN8710
is causing grief to many.

>> but isn't the
>> last patch 5/5 breaking existing setups ?
> 
> IMHO the solution proposed using the PHY_RST_AFTER_CLK_EN was wrong so
> we needed to fix that. Yes we need to take care of DT backward
> compatibility but we still must be able to fix wrong behaviours within
> the driver. I could also argue that PHY_RST_AFTER_CLK_EN solution was
> breaking exisitng setups too.
> 
>> The LAN8710 surely does need
>> clock enabled before the reset line is toggled.
> 
> Yep and therefore you can specify it yet within the DT.

So the idea is that the PHY enables the clock for itself . And if the
MAC doesn't export these clock as clk to which you can refer to in DT,
then you still need the PHY_RST_AFTER_CLK_EN flag, so the MAC can deal
with enabling the clock ? Or is the idea to fix the MAC drivers too ?