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Tue, 24 Dec 2019 13:57:11 +0000 Subject: Re: net: dsa: mv88e6xxx: error parsing ethernet node from dts To: Andrew Lunn Cc: "netdev@vger.kernel.org" , rasmus.villemoes@prevas.dk, Thomas Petazzoni , vivien.didelot@gmail.com References: <27f65072-f3a1-7a3c-5e9e-0cc86d25ab51@televic.com> <20191204153804.GD21904@lunn.ch> <20191204171336.GF21904@lunn.ch> <20191224111929.GD3395@lunn.ch> From: =?UTF-8?Q?J=c3=bcrgen_Lambrecht?= Message-ID: <307c4626-6ea3-39f2-fb34-ba8d9810f905@televic.com> Date: Tue, 24 Dec 2019 14:57:09 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.3.0 In-Reply-To: <20191224111929.GD3395@lunn.ch> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit Content-Language: en-US X-ClientProxiedBy: AM0PR06CA0022.eurprd06.prod.outlook.com (2603:10a6:208:ab::35) To VI1PR07MB5085.eurprd07.prod.outlook.com (2603:10a6:803:9d::13) MIME-Version: 1.0 Received: from [IPv6:2a02:1811:b219:a500:baca:3aff:fed1:9b] (2a02:1811:b219:a500:baca:3aff:fed1:9b) by AM0PR06CA0022.eurprd06.prod.outlook.com (2603:10a6:208:ab::35) with Microsoft SMTP Server (version=TLS1_2, cipher=) via Frontend Transport; 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X-Microsoft-Antispam-Message-Info: lr7ZVL3pOsSHQdp3Epnx9Z8wT+9kr7IOBZGiS/Fm0024PhtrgOwCVpc68TPixBkLY6EHeIcDTj80DwwGuEB4Ra3qJepH2IU55J6mmJsz++q1llnizR1WvyitP5yZnlvWp9S2AOChbue/SPKQucd3EowefLSvchnSaXcZ8tlU2hthPlIG3LLSU2TEBbTosdaFEUy+curRbBm4Gplsf3I8bed88fFbagbBsJQh4wyUZt9hNyMkd71mIoVt+jji7Olb3HujnGWiWlx6Vo/rVlpPDHr5W4skcpVXeLfmp3zJCwWpCa4fuA2LFtn6b8tOePrBTwJHTDWoXV4PHS9kU3a0qn7jZsbTIjiJPpcvvgT8PpBvboC/oJnS2SmVC+jW2VRcJqvC1MHTCUVDF2+i8RM9aPxa+PQ79ceWQvJz5njREDT1iOk9CdqOfS2OpDjaJdw+HrWXwNhlBDLumgeZSDjXZYQ7Q7L8GDFcF/M6IfJmMTutTqhod0dR0RrnWjsXuO7H X-OriginatorOrg: televic.com X-MS-Exchange-CrossTenant-Network-Message-Id: 995fffdd-ef86-463f-5748-08d788792c34 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Dec 2019 13:57:11.1012 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 68a8593e-d1fc-4a6a-b782-1bdcb0633231 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 4wmo6ywjEMDnFXYgRvSbqalRf9WfZ6s7CYWzU8lq33N82po76+wR+smxCoLFiged8nUI/K/12aD84T4912Maug== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR07MB4320 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On 12/24/19 12:19 PM, Andrew Lunn wrote: > CAUTION: This Email originated from outside Televic. Do not click links or open attachments unless you recognize the sender and know the content is safe. > > > On Tue, Dec 24, 2019 at 11:28:27AM +0100, Jürgen Lambrecht wrote: >> On 12/4/19 6:13 PM, Andrew Lunn wrote: >>> But returning 0x0000 is odd. Normally, if an MDIO device does not >>> respond, you read 0xffff, because of the pull up resistor on the bus. >>> >>> The fact you find it ones means it is something like this, some minor >>> configuration problem, power management, etc. >> Hi Adrew, >> >> to close this issue: you were right: the Marvell clock, that comes from the iMX clocking block ENET1_REF_CLK_25M suddenly stops running: >> >> an oscilloscope showed that the Marvell main clock stops shortly after the first probe, and only comes back 5s later at the end of booting when the fixed-phy is configured. >> It is not the fec that stops the clock, because if fec1 is "disabled" also the clock stops, but then does not come back. >> >> We did not found yet how to keep the clock enabled (independent of the fec), so if you have any hints - more than welcome. > Let me make sure i understand your design correct. > > I think you are saying your switch does not have a crystal connected > to XTAL_OUT/XTAL_IN. Instead you want the iMX to generate a 25MHz > clock, which you are feeding to the switch? indeed. > All the designs i've used have the crystal connected to the > switch. The FEC clock line is used as an input, either driven from a > PHY connected to the other FEC port, or the clock output from the > switch. > > So for your design, you need to ensure the 25MHz clock output is > always ticking. Looking at the FEC driver, you see the optional clock > fep->clk_enet_out. This clock is enabled when the FEC interface is > opened, i.e. configured up. It is disabled when the FEC is closed. It > is enabled during probe, but turned off at the end of the probe to > save power. The FEC also has runtime suspend/resume support. This > actually does not touch the clk_enet_out, but it does enable/disable > clocks needed for MDIO to work. I had to fix this many years ago. > > It appears this clock is just a plain SOC clock. > > In imx7d.dtsi we see: > > clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>, > <&clks IMX7D_ENET_AXI_ROOT_CLK>, > <&clks IMX7D_ENET2_TIME_ROOT_CLK>, > <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, > <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; > clock-names = "ipg", "ahb", "ptp", > "enet_clk_ref", "enet_out"; > > The mapping between clock-names and clocks seem a bit odd. But there > is some room for error here, since the FEC driver mostly just enables > them all or disables them all. But you need one specific clock. > > What i suggest you do is add clock support to DSA. Allow DSA to look > up a clock in DT, and call clk_prepare_enable() and > clk_disable_unprepare(). The clock framework uses reference > counting. So if DSA turns a clock on, it does not matter what the FEC > does, it will stay on. It will only go off when all users of the clock > turn it off. > > I'm not sure if this can be done in a generic way for all DSA drivers, > or if you need to add it to the mv88e6xxx driver. The DSA core only > gets involved once the probe of the switch is over. And you probably > need the clock reliably ticking during probe. So maybe it needs to be > in the mv88e6xxx driver. Thanks for the hint. Now I know what to work on next year :-), because we are closed now for a week. Jürgen > :- > Andrew