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[72.194.116.95]) by smtp.gmail.com with ESMTPSA id o11sm12949904pgj.33.2022.01.24.09.34.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Jan 2022 09:34:25 -0800 (PST) Message-ID: <4fd93933-9b98-175a-d6f2-8cb3ddc30c51@gmail.com> Date: Mon, 24 Jan 2022 09:34:23 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: MT7621 SoC Traffic Won't Flow on RGMII2 Bus/2nd GMAC Content-Language: en-US To: "Russell King (Oracle)" Cc: Andrew Lunn , =?UTF-8?B?QXLEsW7DpyDDnE5BTA==?= , DENG Qingfang , Luiz Angelo Daros de Luca , Matthias Brugger , John Crispin , Siddhant Gupta , Ilya Lipnitskiy , Sergio Paracuellos , Felix Fietkau , Sean Wang , Mark Lee , Jakub Kicinski , David Miller , =?UTF-8?Q?Ren=c3=a9_van_Dorst?= , "moderated list:ARM/Mediatek SoC support" , netdev , linux-mips@vger.kernel.org, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , openwrt-devel@lists.openwrt.org, erkin.bozoglu@xeront.com References: <83a35aa3-6cb8-2bc4-2ff4-64278bbcd8c8@arinc9.com> <02ecce91-7aad-4392-c9d7-f45ca1b31e0b@arinc9.com> From: Florian Fainelli In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On 1/24/2022 9:26 AM, Russell King (Oracle) wrote: > On Mon, Jan 24, 2022 at 09:13:38AM -0800, Florian Fainelli wrote: >> On 1/23/2022 7:26 AM, Andrew Lunn wrote: >>> On Sun, Jan 23, 2022 at 11:33:04AM +0300, Arınç ÜNAL wrote: >>>> Hey Deng, >>>> >>>> On 23/01/2022 09:51, DENG Qingfang wrote: >>>>> Hi, >>>>> >>>>> Do you set the ethernet pinmux correctly? >>>>> >>>>> ðernet { >>>>> pinctrl-names = "default"; >>>>> pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>; >>>>> }; >>>> >>>> This fixed it! We did have &rgmii2_pins on the gmac1 node (it was originally >>>> on external_phy) so we never thought to investigate the pinctrl >>>> configuration further! Turns out &rgmii2_pins needs to be defined on the >>>> ethernet node instead. >>> >>> PHYs are generally external, so pinmux on them makes no sense. PHYs in >>> DT are not devices in the usual sense, so i don't think the driver >>> core will handle pinmux for them, even if you did list them. >> >> Not sure I understand your comment here, this is configuring the pinmux on >> the SoC side in order for the second RGMII interface's data path to work. > > The pinmux configuration was listed under the external PHY node, which > is qutie unusual. In the case of phylib and external ethernet PHYs, > this can be a problem. > > The pinmux configuration is normally handled at device probe time by > the device model, but remember phylib bypasses that when it attaches > the generic PHY driver - meaning you don't get the pinmux configured. > > What this means is that pinmux configuration in ethernet PHY nodes is > unreliable. It will only happen if we have a specific driver for the > PHY and the driver model binds that driver. > > Of course, if we killed the generic driver, that would get around this > issue by requiring every PHY to have its own specific driver, but there > would be many complaints because likely lots would stop working. I suppose that explains why this is still in staging then :) Andrew's answer makes more sense now, thanks. -- Florian