From mboxrd@z Thu Jan  1 00:00:00 1970
From: Giuseppe CAVALLARO <peppe.cavallaro@st.com>
Subject: Re: [PATCH 2/5] stmmac: pci: use managed resources
Date: Mon, 27 Oct 2014 16:28:06 +0100
Message-ID: <544E6486.6040502@st.com>
References: <1413909333-16380-1-git-send-email-andriy.shevchenko@linux.intel.com>	 <1413909333-16380-3-git-send-email-andriy.shevchenko@linux.intel.com>	 <5446C827.2040801@cogentembedded.com> <1413966993.2396.26.camel@linux.intel.com>
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Cc: <netdev@vger.kernel.org>,
	Kweh Hock Leong <hock.leong.kweh@intel.com>,
	"David S. Miller" <davem@davemloft.net>,
	Vince Bridgers <vbridgers2013@gmail.com>,
	Rayagond K <rayagond@vayavyalabs.com>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
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On 10/22/2014 10:36 AM, Andy Shevchenko wrote:
> So, I was trying to find any specification on public regarding to boards
> that have this IP, no luck so far. I guess that that code was created
> due to XILINX FPGA usage which probably can provide any BAR user wants
> to. Thus, I imply that in real applications the BAR most probably will
> be 0. However, I left variable which can be overridden in future
> (regarding to PCI ID).
>
> It would be nice to hear someone from ST about this. Giuseppe?

Hello Andy

this chip is on ST SoCs since long time but embedded. I have no PCI
card. Added Rayagond on copy too

peppe