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Miller" CC: "netdev@vger.kernel.org" , Igor Russkikh , Nikita Danilov Subject: [PATCH v2 net-next 5/6] net: aquantia: replace AQ_HW_WAIT_FOR with readx_poll_timeout_atomic Thread-Topic: [PATCH v2 net-next 5/6] net: aquantia: replace AQ_HW_WAIT_FOR with readx_poll_timeout_atomic Thread-Index: AQHUzpVjTndyVoRyC0CP//MEXuYhQw== Date: Wed, 27 Feb 2019 12:10:11 +0000 Message-ID: <5d103a36d70a35311cc2c5c847fe42b2a7a93bbc.1551269343.git.igor.russkikh@aquantia.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BYAPR01CA0032.prod.exchangelabs.com (2603:10b6:a02:80::45) To DM6PR11MB3625.namprd11.prod.outlook.com (2603:10b6:5:13a::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 18bbdcc2-d708-43b4-d532-08d69cac85b3 x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600127)(711020)(4605104)(2017052603328)(7153060)(7193020);SRVR:DM6PR11MB4009; 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received-spf: None (protection.outlook.com: aquantia.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 33bynHaMinodz1jBmPmAP1ypM3iAQtaeVYGQIsEDy7JYlu/cAiZfDQjHsR8EJUru6Ijo7mudZ0YeJpo/AKQr3WLJoxOcErbQCEb7iV5TEmFu/A0GNTgr6MfmTyULZ+Hj8w5TE9E+Qm+1au6ek/+CvdGH+ZuXQY51NaOzD59vEal2ASvj8Y8GR2Ex5SB4BJHcrSfl9M/+Nuf/2rT8rAGicbByTW4wrsm/jl+uQcHKgvZBp2kZK2HKp9eQTORsIRd8rveFTF4SV2YnDu55oUqdB8TXzrke2WBzQ3VE4vztmQfw5P6YN3n/cKtfrPGpMzIS+gxUbHhSwN4DT/tCLoPEmgrGzsMQqFqDg80sJmDNoLbj+tYVRv7jW1YXXrrP86H+bJHqdYGJ8pNFJuIpNy4RWUReytPANn0rac4AP/Xev1w= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 18bbdcc2-d708-43b4-d532-08d69cac85b3 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Feb 2019 12:10:09.6807 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB4009 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Nikita Danilov David noticed the original define was hiding 'err' variable reference. Thats confusing and counterintuitive. Andrew noted the whole macro could be replaced with standard readx_poll kernel macro. This makes code more readable. Signed-off-by: Nikita Danilov Signed-off-by: Igor Russkikh --- .../ethernet/aquantia/atlantic/aq_hw_utils.h | 14 +-- .../aquantia/atlantic/hw_atl/hw_atl_a0.c | 21 +++- .../aquantia/atlantic/hw_atl/hw_atl_b0.c | 12 +- .../aquantia/atlantic/hw_atl/hw_atl_llh.c | 21 ++++ .../aquantia/atlantic/hw_atl/hw_atl_llh.h | 12 ++ .../atlantic/hw_atl/hw_atl_llh_internal.h | 2 + .../aquantia/atlantic/hw_atl/hw_atl_utils.c | 110 +++++++++++++----- .../atlantic/hw_atl/hw_atl_utils_fw2x.c | 64 +++++++--- 8 files changed, 184 insertions(+), 72 deletions(-) diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h b/drivers= /net/ethernet/aquantia/atlantic/aq_hw_utils.h index dc88a1221f1d..bc711238ca0c 100644 --- a/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h +++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h @@ -14,6 +14,8 @@ #ifndef AQ_HW_UTILS_H #define AQ_HW_UTILS_H =20 +#include + #include "aq_common.h" =20 #ifndef HIDWORD @@ -23,18 +25,6 @@ =20 #define AQ_HW_SLEEP(_US_) mdelay(_US_) =20 -#define AQ_HW_WAIT_FOR(_B_, _US_, _N_) \ -do { \ - unsigned int AQ_HW_WAIT_FOR_i; \ - for (AQ_HW_WAIT_FOR_i =3D _N_; (!(_B_)) && (AQ_HW_WAIT_FOR_i);\ - --AQ_HW_WAIT_FOR_i) {\ - udelay(_US_); \ - } \ - if (!AQ_HW_WAIT_FOR_i) {\ - err =3D -ETIME; \ - } \ -} while (0) - #define aq_pr_err(...) pr_err(AQ_CFG_DRV_NAME ": " __VA_ARGS__) #define aq_pr_trace(...) pr_info(AQ_CFG_DRV_NAME ": " __VA_ARGS__) =20 diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c b/dr= ivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c index 30fdcb9b11fd..f6f8338153a2 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c @@ -85,6 +85,7 @@ const struct aq_hw_caps_s hw_atl_a0_caps_aqc109 =3D { static int hw_atl_a0_hw_reset(struct aq_hw_s *self) { int err =3D 0; + u32 val; =20 hw_atl_glb_glb_reg_res_dis_set(self, 1U); hw_atl_pci_pci_reg_res_dis_set(self, 0U); @@ -95,7 +96,9 @@ static int hw_atl_a0_hw_reset(struct aq_hw_s *self) hw_atl_glb_soft_res_set(self, 1); =20 /* check 10 times by 1ms */ - AQ_HW_WAIT_FOR(hw_atl_glb_soft_res_get(self) =3D=3D 0, 1000U, 10U); + err =3D readx_poll_timeout_atomic(hw_atl_glb_soft_res_get, + self, val, val =3D=3D 0, + 1000U, 10000U); if (err < 0) goto err_exit; =20 @@ -103,7 +106,9 @@ static int hw_atl_a0_hw_reset(struct aq_hw_s *self) hw_atl_itr_res_irq_set(self, 1U); =20 /* check 10 times by 1ms */ - AQ_HW_WAIT_FOR(hw_atl_itr_res_irq_get(self) =3D=3D 0, 1000U, 10U); + err =3D readx_poll_timeout_atomic(hw_atl_itr_res_irq_get, + self, val, val =3D=3D 0, + 1000U, 10000U); if (err < 0) goto err_exit; =20 @@ -181,6 +186,7 @@ static int hw_atl_a0_hw_rss_hash_set(struct aq_hw_s *se= lf, int err =3D 0; unsigned int i =3D 0U; unsigned int addr =3D 0U; + u32 val; =20 for (i =3D 10, addr =3D 0U; i--; ++addr) { u32 key_data =3D cfg->is_rss ? @@ -188,8 +194,9 @@ static int hw_atl_a0_hw_rss_hash_set(struct aq_hw_s *se= lf, hw_atl_rpf_rss_key_wr_data_set(self, key_data); hw_atl_rpf_rss_key_addr_set(self, addr); hw_atl_rpf_rss_key_wr_en_set(self, 1U); - AQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) =3D=3D 0, - 1000U, 10U); + err =3D readx_poll_timeout_atomic(hw_atl_rpf_rss_key_wr_en_get, + self, val, val =3D=3D 0, + 1000U, 10000U); if (err < 0) goto err_exit; } @@ -209,6 +216,7 @@ static int hw_atl_a0_hw_rss_set(struct aq_hw_s *self, int err =3D 0; u16 bitary[1 + (HW_ATL_A0_RSS_REDIRECTION_MAX * HW_ATL_A0_RSS_REDIRECTION_BITS / 16U)]; + u32 val; =20 memset(bitary, 0, sizeof(bitary)); =20 @@ -222,8 +230,9 @@ static int hw_atl_a0_hw_rss_set(struct aq_hw_s *self, hw_atl_rpf_rss_redir_tbl_wr_data_set(self, bitary[i]); hw_atl_rpf_rss_redir_tbl_addr_set(self, i); hw_atl_rpf_rss_redir_wr_en_set(self, 1U); - AQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) =3D=3D 0, - 1000U, 10U); + err =3D readx_poll_timeout_atomic(hw_atl_rpf_rss_redir_wr_en_get, + self, val, val =3D=3D 0, + 1000U, 10000U); if (err < 0) goto err_exit; } diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c b/dr= ivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c index c4cdc51350b2..7eb5ea948d61 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c @@ -173,6 +173,7 @@ static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *se= lf, int err =3D 0; unsigned int i =3D 0U; unsigned int addr =3D 0U; + u32 val; =20 for (i =3D 10, addr =3D 0U; i--; ++addr) { u32 key_data =3D cfg->is_rss ? @@ -180,8 +181,9 @@ static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *se= lf, hw_atl_rpf_rss_key_wr_data_set(self, key_data); hw_atl_rpf_rss_key_addr_set(self, addr); hw_atl_rpf_rss_key_wr_en_set(self, 1U); - AQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) =3D=3D 0, - 1000U, 10U); + err =3D readx_poll_timeout_atomic(hw_atl_rpf_rss_key_wr_en_get, + self, val, val =3D=3D 0, + 1000U, 10000U); if (err < 0) goto err_exit; } @@ -201,6 +203,7 @@ static int hw_atl_b0_hw_rss_set(struct aq_hw_s *self, int err =3D 0; u16 bitary[1 + (HW_ATL_B0_RSS_REDIRECTION_MAX * HW_ATL_B0_RSS_REDIRECTION_BITS / 16U)]; + u32 val; =20 memset(bitary, 0, sizeof(bitary)); =20 @@ -214,8 +217,9 @@ static int hw_atl_b0_hw_rss_set(struct aq_hw_s *self, hw_atl_rpf_rss_redir_tbl_wr_data_set(self, bitary[i]); hw_atl_rpf_rss_redir_tbl_addr_set(self, i); hw_atl_rpf_rss_redir_wr_en_set(self, 1U); - AQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) =3D=3D 0, - 1000U, 10U); + err =3D readx_poll_timeout_atomic(hw_atl_rpf_rss_redir_wr_en_get, + self, val, val =3D=3D 0, + 1000U, 10000U); if (err < 0) goto err_exit; } diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c b/d= rivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c index 939f77e2e117..f72194c77f5f 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c @@ -1585,3 +1585,24 @@ void hw_atl_rpfl3l4_ipv6_dest_addr_set(struct aq_hw_= s *aq_hw, u8 location, HW_ATL_RPF_L3_DSTA_ADR(location + i), ipv6_dest[i]); } + +u32 hw_atl_sem_ram_get(struct aq_hw_s *self) +{ + return hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM); +} + +u32 hw_atl_scrpad_get(struct aq_hw_s *aq_hw, u32 scratch_scp) +{ + return aq_hw_read_reg(aq_hw, + HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp)); +} + +u32 hw_atl_scrpad12_get(struct aq_hw_s *self) +{ + return hw_atl_scrpad_get(self, 0xB); +} + +u32 hw_atl_scrpad25_get(struct aq_hw_s *self) +{ + return hw_atl_scrpad_get(self, 0x18); +} diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h b/d= rivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h index 03c570d115fe..40e6c1e44b5b 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h @@ -752,4 +752,16 @@ void hw_atl_rpfl3l4_ipv6_src_addr_set(struct aq_hw_s *= aq_hw, u8 location, void hw_atl_rpfl3l4_ipv6_dest_addr_set(struct aq_hw_s *aq_hw, u8 location, u32 *ipv6_dest); =20 +/* get global microprocessor ram semaphore */ +u32 hw_atl_sem_ram_get(struct aq_hw_s *self); + +/* get global microprocessor scratch pad register */ +u32 hw_atl_scrpad_get(struct aq_hw_s *aq_hw, u32 scratch_scp); + +/* get global microprocessor scratch pad 12 register */ +u32 hw_atl_scrpad12_get(struct aq_hw_s *self); + +/* get global microprocessor scratch pad 25 register */ +u32 hw_atl_scrpad25_get(struct aq_hw_s *self); + #endif /* HW_ATL_LLH_H */ diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_inter= nal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h index 8470d92db812..50b4dee5562d 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h @@ -2519,4 +2519,6 @@ /* Default value of bitfield l3_da0[1F:0] */ #define HW_ATL_RPF_L3_DSTA_DEFAULT 0x0 =20 +#define HW_ATL_FW_SM_RAM 0x2U + #endif /* HW_ATL_LLH_INTERNAL_H */ diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c b= /drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c index 9b74a3197d7f..e5df40b00afd 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c @@ -25,7 +25,9 @@ #define HW_ATL_MIF_ADDR 0x0208U #define HW_ATL_MIF_VAL 0x020CU =20 -#define HW_ATL_FW_SM_RAM 0x2U +#define HW_ATL_RPC_CONTROL_ADR 0x0338U +#define HW_ATL_RPC_STATE_ADR 0x033CU + #define HW_ATL_MPI_FW_VERSION 0x18 #define HW_ATL_MPI_CONTROL_ADR 0x0368U #define HW_ATL_MPI_STATE_ADR 0x036CU @@ -53,6 +55,12 @@ static int hw_atl_utils_ver_match(u32 ver_expected, u32 = ver_actual); static int hw_atl_utils_mpi_set_state(struct aq_hw_s *self, enum hal_atl_utils_fw_state_e state); =20 +static u32 hw_atl_utils_get_mpi_mbox_tid(struct aq_hw_s *self); +static u32 hw_atl_utils_mpi_get_state(struct aq_hw_s *self); +static u32 hw_atl_utils_mif_cmd_get(struct aq_hw_s *self); +static u32 hw_atl_utils_mif_addr_get(struct aq_hw_s *self); +static u32 hw_atl_utils_rpc_state_get(struct aq_hw_s *self); + int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_= ops) { int err =3D 0; @@ -234,6 +242,7 @@ int hw_atl_utils_soft_reset(struct aq_hw_s *self) { int k; u32 boot_exit_code =3D 0; + u32 val; =20 for (k =3D 0; k < 1000; ++k) { u32 flb_status =3D aq_hw_read_reg(self, @@ -260,9 +269,11 @@ int hw_atl_utils_soft_reset(struct aq_hw_s *self) int err =3D 0; =20 hw_atl_utils_mpi_set_state(self, MPI_DEINIT); - AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_MPI_STATE_ADR) & - HW_ATL_MPI_STATE_MSK) =3D=3D MPI_DEINIT, - 10, 1000U); + err =3D readx_poll_timeout_atomic(hw_atl_utils_mpi_get_state, + self, val, + (val & HW_ATL_MPI_STATE_MSK) =3D=3D + MPI_DEINIT, + 10, 10000U); if (err) return err; } @@ -277,10 +288,11 @@ int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *sel= f, u32 a, u32 *p, u32 cnt) { int err =3D 0; + u32 val; =20 - AQ_HW_WAIT_FOR(hw_atl_reg_glb_cpu_sem_get(self, - HW_ATL_FW_SM_RAM) =3D=3D 1U, - 1U, 10000U); + err =3D readx_poll_timeout_atomic(hw_atl_sem_ram_get, + self, val, val =3D=3D 1U, + 1U, 10000U); =20 if (err < 0) { bool is_locked; @@ -299,13 +311,14 @@ int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *sel= f, u32 a, aq_hw_write_reg(self, HW_ATL_MIF_CMD, 0x00008000U); =20 if (IS_CHIP_FEATURE(REVISION_B1)) - AQ_HW_WAIT_FOR(a !=3D aq_hw_read_reg(self, - HW_ATL_MIF_ADDR), - 1, 1000U); + err =3D readx_poll_timeout_atomic(hw_atl_utils_mif_addr_get, + self, val, val !=3D a, + 1U, 1000U); else - AQ_HW_WAIT_FOR(!(0x100 & aq_hw_read_reg(self, - HW_ATL_MIF_CMD)), - 1, 1000U); + err =3D readx_poll_timeout_atomic(hw_atl_utils_mif_cmd_get, + self, val, + !(val & 0x100), + 1U, 1000U); =20 *(p++) =3D aq_hw_read_reg(self, HW_ATL_MIF_VAL); a +=3D 4; @@ -320,6 +333,7 @@ int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self,= u32 a, static int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 = *p, u32 cnt) { + u32 val; int err =3D 0; bool is_locked; =20 @@ -337,10 +351,11 @@ static int hw_atl_utils_fw_upload_dwords(struct aq_hw= _s *self, u32 a, u32 *p, (0x80000000 | (0xFFFF & (offset * 4)))); hw_atl_mcp_up_force_intr_set(self, 1); /* 1000 times by 10us =3D 10ms */ - AQ_HW_WAIT_FOR((aq_hw_read_reg(self, - 0x32C) & 0xF0000000) !=3D - 0x80000000, - 10, 1000); + err =3D readx_poll_timeout_atomic(hw_atl_scrpad12_get, + self, val, + (val & 0xF0000000) =3D=3D + 0x80000000, + 10U, 10000U); } } else { u32 offset =3D 0; @@ -351,8 +366,10 @@ static int hw_atl_utils_fw_upload_dwords(struct aq_hw_= s *self, u32 a, u32 *p, aq_hw_write_reg(self, 0x20C, p[offset]); aq_hw_write_reg(self, 0x200, 0xC000); =20 - AQ_HW_WAIT_FOR((aq_hw_read_reg(self, 0x200U) & - 0x100) =3D=3D 0, 10, 1000); + err =3D readx_poll_timeout_atomic(hw_atl_utils_mif_cmd_get, + self, val, + (val & 0x100) =3D=3D 0, + 1000U, 10000U); } } =20 @@ -395,15 +412,14 @@ static int hw_atl_utils_init_ucp(struct aq_hw_s *self= , hw_atl_reg_glb_cpu_scratch_scp_set(self, 0x00000000U, 25U); =20 /* check 10 times by 1ms */ - AQ_HW_WAIT_FOR(0U !=3D (self->mbox_addr =3D - aq_hw_read_reg(self, 0x360U)), 1000U, 10U); + err =3D readx_poll_timeout_atomic(hw_atl_scrpad25_get, + self, self->mbox_addr, + self->mbox_addr !=3D 0U, + 1000U, 10000U); =20 return err; } =20 -#define HW_ATL_RPC_CONTROL_ADR 0x0338U -#define HW_ATL_RPC_STATE_ADR 0x033CU - struct aq_hw_atl_utils_fw_rpc_tid_s { union { u32 val; @@ -452,10 +468,10 @@ int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self, =20 self->rpc_tid =3D sw.tid; =20 - AQ_HW_WAIT_FOR(sw.tid =3D=3D - (fw.val =3D - aq_hw_read_reg(self, HW_ATL_RPC_STATE_ADR), - fw.tid), 1000U, 100U); + err =3D readx_poll_timeout_atomic(hw_atl_utils_rpc_state_get, + self, fw.val, + sw.tid =3D=3D fw.tid, + 1000U, 100000U); =20 if (fw.len =3D=3D 0xFFFFU) { err =3D hw_atl_utils_fw_rpc_call(self, sw.len); @@ -559,10 +575,11 @@ static int hw_atl_utils_mpi_set_state(struct aq_hw_s = *self, =20 transaction_id =3D mbox.transaction_id; =20 - AQ_HW_WAIT_FOR(transaction_id !=3D - (hw_atl_utils_mpi_read_mbox(self, &mbox), - mbox.transaction_id), - 1000U, 100U); + err =3D readx_poll_timeout_atomic(hw_atl_utils_get_mpi_mbox_tid, + self, mbox.transaction_id, + transaction_id !=3D + mbox.transaction_id, + 1000U, 100000U); if (err < 0) goto err_exit; } @@ -905,6 +922,35 @@ static int aq_fw1x_set_power(struct aq_hw_s *self, uns= igned int power_state, return err; } =20 +static u32 hw_atl_utils_get_mpi_mbox_tid(struct aq_hw_s *self) +{ + struct hw_atl_utils_mbox_header mbox; + + hw_atl_utils_mpi_read_mbox(self, &mbox); + + return mbox.transaction_id; +} + +static u32 hw_atl_utils_mpi_get_state(struct aq_hw_s *self) +{ + return aq_hw_read_reg(self, HW_ATL_MPI_STATE_ADR); +} + +static u32 hw_atl_utils_mif_cmd_get(struct aq_hw_s *self) +{ + return aq_hw_read_reg(self, HW_ATL_MIF_CMD); +} + +static u32 hw_atl_utils_mif_addr_get(struct aq_hw_s *self) +{ + return aq_hw_read_reg(self, HW_ATL_MIF_ADDR); +} + +static u32 hw_atl_utils_rpc_state_get(struct aq_hw_s *self) +{ + return aq_hw_read_reg(self, HW_ATL_RPC_STATE_ADR); +} + const struct aq_fw_ops aq_fw_1x_ops =3D { .init =3D hw_atl_utils_mpi_create, .deinit =3D hw_atl_fw1x_deinit, diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2= x.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c index 7de3220d9cab..c628290d7546 100644 --- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c +++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c @@ -20,15 +20,14 @@ #include "hw_atl_utils.h" #include "hw_atl_llh.h" =20 -#define HW_ATL_FW2X_MPI_EFUSE_ADDR 0x364 -#define HW_ATL_FW2X_MPI_MBOX_ADDR 0x360 #define HW_ATL_FW2X_MPI_RPC_ADDR 0x334 =20 +#define HW_ATL_FW2X_MPI_MBOX_ADDR 0x360 +#define HW_ATL_FW2X_MPI_EFUSE_ADDR 0x364 #define HW_ATL_FW2X_MPI_CONTROL_ADDR 0x368 #define HW_ATL_FW2X_MPI_CONTROL2_ADDR 0x36C - #define HW_ATL_FW2X_MPI_STATE_ADDR 0x370 -#define HW_ATL_FW2X_MPI_STATE2_ADDR 0x374 +#define HW_ATL_FW2X_MPI_STATE2_ADDR 0x374 =20 #define HW_ATL_FW2X_CAP_PAUSE BIT(CAPS_HI_PAUSE) #define HW_ATL_FW2X_CAP_ASYM_PAUSE BIT(CAPS_HI_ASYMMETRIC_PAUSE) @@ -72,17 +71,24 @@ static int aq_fw2x_set_link_speed(struct aq_hw_s *self,= u32 speed); static int aq_fw2x_set_state(struct aq_hw_s *self, enum hal_atl_utils_fw_state_e state); =20 +static u32 aq_fw2x_mbox_get(struct aq_hw_s *self); +static u32 aq_fw2x_rpc_get(struct aq_hw_s *self); +static u32 aq_fw2x_state2_get(struct aq_hw_s *self); + static int aq_fw2x_init(struct aq_hw_s *self) { int err =3D 0; =20 /* check 10 times by 1ms */ - AQ_HW_WAIT_FOR(0U !=3D (self->mbox_addr =3D - aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR)), - 1000U, 10U); - AQ_HW_WAIT_FOR(0U !=3D (self->rpc_addr =3D - aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR)), - 1000U, 100U); + err =3D readx_poll_timeout_atomic(aq_fw2x_mbox_get, + self, self->mbox_addr, + self->mbox_addr !=3D 0U, + 1000U, 10000U); + + err =3D readx_poll_timeout_atomic(aq_fw2x_rpc_get, + self, self->rpc_addr, + self->rpc_addr !=3D 0U, + 1000U, 100000U); =20 return err; } @@ -286,16 +292,18 @@ static int aq_fw2x_update_stats(struct aq_hw_s *self) int err =3D 0; u32 mpi_opts =3D aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR); u32 orig_stats_val =3D mpi_opts & BIT(CAPS_HI_STATISTICS); + u32 stats_val; =20 /* Toggle statistics bit for FW to update */ mpi_opts =3D mpi_opts ^ BIT(CAPS_HI_STATISTICS); aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); =20 /* Wait FW to report back */ - AQ_HW_WAIT_FOR(orig_stats_val !=3D - (aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) & - BIT(CAPS_HI_STATISTICS)), - 1U, 10000U); + err =3D readx_poll_timeout_atomic(aq_fw2x_state2_get, + self, stats_val, + orig_stats_val !=3D (stats_val & + BIT(CAPS_HI_STATISTICS)), + 1U, 10000U); if (err) return err; =20 @@ -309,6 +317,7 @@ static int aq_fw2x_set_sleep_proxy(struct aq_hw_s *self= , u8 *mac) unsigned int rpc_size =3D 0U; u32 mpi_opts; int err =3D 0; + u32 val; =20 rpc_size =3D sizeof(rpc->msg_id) + sizeof(*cfg); =20 @@ -337,8 +346,10 @@ static int aq_fw2x_set_sleep_proxy(struct aq_hw_s *sel= f, u8 *mac) mpi_opts |=3D HW_ATL_FW2X_CTRL_SLEEP_PROXY; aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); =20 - AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) & - HW_ATL_FW2X_CTRL_SLEEP_PROXY), 1U, 10000U); + err =3D readx_poll_timeout_atomic(aq_fw2x_state2_get, + self, val, + val & HW_ATL_FW2X_CTRL_SLEEP_PROXY, + 1U, 10000U); =20 err_exit: return err; @@ -350,6 +361,7 @@ static int aq_fw2x_set_wol_params(struct aq_hw_s *self,= u8 *mac) struct fw2x_msg_wol *msg =3D NULL; u32 mpi_opts; int err =3D 0; + u32 val; =20 err =3D hw_atl_utils_fw_rpc_wait(self, &rpc); if (err < 0) @@ -374,8 +386,9 @@ static int aq_fw2x_set_wol_params(struct aq_hw_s *self,= u8 *mac) mpi_opts |=3D HW_ATL_FW2X_CTRL_WOL; aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts); =20 - AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) & - HW_ATL_FW2X_CTRL_WOL), 1U, 10000U); + err =3D readx_poll_timeout_atomic(aq_fw2x_state2_get, + self, val, val & HW_ATL_FW2X_CTRL_WOL, + 1U, 10000U); =20 err_exit: return err; @@ -471,6 +484,21 @@ static u32 aq_fw2x_get_flow_control(struct aq_hw_s *se= lf, u32 *fcmode) return 0; } =20 +static u32 aq_fw2x_mbox_get(struct aq_hw_s *self) +{ + return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR); +} + +static u32 aq_fw2x_rpc_get(struct aq_hw_s *self) +{ + return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR); +} + +static u32 aq_fw2x_state2_get(struct aq_hw_s *self) +{ + return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR); +} + const struct aq_fw_ops aq_fw_2x_ops =3D { .init =3D aq_fw2x_init, .deinit =3D aq_fw2x_deinit, --=20 2.17.1