Re: [PATCH net-next v3 1/2] net: macb: move the Tx and Rx buffer initialization into a function

[<Nicolas.Ferre@microchip.com>]

On 13/11/2019 at 10:00, Antoine Tenart wrote:
> External E-Mail
> 
> 
> This patch moves the Tx and Rx buffer initialization into its own
> function. This does not modify the behaviour of the driver and will be
> helpful to convert the driver to phylink.
> 
> Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>

Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>

> ---
>   drivers/net/ethernet/cadence/macb_main.c | 39 +++++++++++++++---------
>   1 file changed, 24 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
> index b884cf7f339b..1b3c8d678116 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
> @@ -388,6 +388,27 @@ static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
>   	return status;
>   }
>   
> +static void macb_init_buffers(struct macb *bp)
> +{
> +	struct macb_queue *queue;
> +	unsigned int q;
> +
> +	for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
> +		queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
> +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
> +		if (bp->hw_dma_cap & HW_DMA_CAP_64B)
> +			queue_writel(queue, RBQPH,
> +				     upper_32_bits(queue->rx_ring_dma));
> +#endif
> +		queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
> +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
> +		if (bp->hw_dma_cap & HW_DMA_CAP_64B)
> +			queue_writel(queue, TBQPH,
> +				     upper_32_bits(queue->tx_ring_dma));
> +#endif
> +	}
> +}
> +
>   /**
>    * macb_set_tx_clk() - Set a clock to a new frequency
>    * @clk		Pointer to the clock to change
> @@ -1314,26 +1335,14 @@ static void macb_hresp_error_task(unsigned long data)
>   	bp->macbgem_ops.mog_init_rings(bp);
>   
>   	/* Initialize TX and RX buffers */
> -	for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
> -		queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
> -#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
> -		if (bp->hw_dma_cap & HW_DMA_CAP_64B)
> -			queue_writel(queue, RBQPH,
> -				     upper_32_bits(queue->rx_ring_dma));
> -#endif
> -		queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
> -#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
> -		if (bp->hw_dma_cap & HW_DMA_CAP_64B)
> -			queue_writel(queue, TBQPH,
> -				     upper_32_bits(queue->tx_ring_dma));
> -#endif
> +	macb_init_buffers(bp);
>   
> -		/* Enable interrupts */
> +	/* Enable interrupts */
> +	for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
>   		queue_writel(queue, IER,
>   			     bp->rx_intr_mask |
>   			     MACB_TX_INT_FLAGS |
>   			     MACB_BIT(HRESP));
> -	}
>   
>   	ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
>   	macb_writel(bp, NCR, ctrl);
> 


-- 
Nicolas Ferre