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Thu, 21 May 2020 03:15:28 +0000 From: Andy Duan To: Andrew Lunn CC: "davem@davemloft.net" , "netdev@vger.kernel.org" , "martin.fuzzey@flowbird.group" , "robh+dt@kernel.org" , "shawnguo@kernel.org" , "devicetree@vger.kernel.org" Subject: RE: [EXT] Re: [PATCH net 3/4] ARM: dts: imx6: update fec gpr property to match new format Thread-Topic: [EXT] Re: [PATCH net 3/4] ARM: dts: imx6: update fec gpr property to match new format Thread-Index: AQHWLoHSZsTKfn2KY0W5vmilgDZ/AqixNB4AgACoEqA= Date: Thu, 21 May 2020 03:15:28 +0000 Message-ID: References: <1589963516-26703-1-git-send-email-fugang.duan@nxp.com> <1589963516-26703-4-git-send-email-fugang.duan@nxp.com> <20200520170322.GJ652285@lunn.ch> In-Reply-To: <20200520170322.GJ652285@lunn.ch> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: lunn.ch; dkim=none (message not signed) header.d=none;lunn.ch; dmarc=none action=none header.from=nxp.com; x-originating-ip: [119.31.174.66] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: a5c45306-47d5-43a5-d331-08d7fd353672 x-ms-traffictypediagnostic: AM6PR0402MB3431: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:4941; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: a5c45306-47d5-43a5-d331-08d7fd353672 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 May 2020 03:15:28.3753 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: J8CPhIlxmQcgdw6rDljly3bWZfYJ0GpT4A52cVYiuguhI/JMiYTrdtH9oR18nc4HVXMELwUIc04UumsOvKycng== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR0402MB3431 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Andrew Lunn Sent: Thursday, May 21, 2020 1:03 AM > On Wed, May 20, 2020 at 04:31:55PM +0800, fugang.duan@nxp.com wrote: > > From: Fugang Duan > > > > Update the gpr property to define gpr register offset and bit in DT. > > > > Signed-off-by: Fugang Duan > > --- > > arch/arm/boot/dts/imx6qdl.dtsi | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/arch/arm/boot/dts/imx6qdl.dtsi > > b/arch/arm/boot/dts/imx6qdl.dtsi index 98da446..a4a68b7 100644 > > --- a/arch/arm/boot/dts/imx6qdl.dtsi > > +++ b/arch/arm/boot/dts/imx6qdl.dtsi > > @@ -1045,7 +1045,7 @@ > > <&clks > IMX6QDL_CLK_ENET>, > > <&clks > IMX6QDL_CLK_ENET_REF>; > > clock-names =3D "ipg", "ahb", "ptp"; > > - gpr =3D <&gpr>; > > + gpr =3D <&gpr 0x34 27>; > > status =3D "disabled"; > > }; >=20 > Hi Andy >=20 > This is the same values as hard coded, so no change here. >=20 > The next patch does not use grp at all. So it is unclear to me if you act= ually > make use of what you just added. I don't see anywhere >=20 > gpr =3D <&gpr 0x42 24>; >=20 > which is the whole point of this change, being able to specify different = values. >=20 > Andrew Andrew, patch#1 in the series will parse the property to get register offse= t and bit. Patch#2 describes the property format as below: <&gpr req_gpr req_bit>. gpr is the phandle to general purpose register node. req_gpr is the gpr register offset for ENET stop request. req_bit is the gpr bit offset for ENET stop request. All i.MX support wake-on-lan, imx6q/dl/qp is the first platforms in upstrea= m to support it. As you know, most of i.MX chips has two ethernet instances, they have diffe= rent gpr bit. gpr is used to enter/exit stop mode for soc. So it can be defined in dtsi f= ile. "fsl,magic-packet;" property is define the board wakeup capability. I am not sure whether above information is clear for you why to add the pat= ch set. Andy