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Thu, 21 May 2020 02:40:14 +0000 From: Andy Duan To: Jakub Kicinski CC: "davem@davemloft.net" , "netdev@vger.kernel.org" , "martin.fuzzey@flowbird.group" , "robh+dt@kernel.org" , "shawnguo@kernel.org" , "devicetree@vger.kernel.org" Subject: RE: [EXT] Re: [PATCH net 1/4] net: ethernet: fec: move GPR register offset and bit into DT Thread-Topic: [EXT] Re: [PATCH net 1/4] net: ethernet: fec: move GPR register offset and bit into DT Thread-Index: AQHWLoHPjdUrXObnOkaNyQWAWrHig6ixMaOAgACjaQA= Date: Thu, 21 May 2020 02:40:13 +0000 Message-ID: References: <1589963516-26703-1-git-send-email-fugang.duan@nxp.com> <1589963516-26703-2-git-send-email-fugang.duan@nxp.com> <20200520095430.05cffcee@kicinski-fedora-pc1c0hjn.dhcp.thefacebook.com> In-Reply-To: <20200520095430.05cffcee@kicinski-fedora-pc1c0hjn.dhcp.thefacebook.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; 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x-ms-exchange-antispam-messagedata: N1J4U63ZYDrxoLEsZfUjDV41r4Uk93SGdoTtubZySUwNn4tf+/zx3/zd0MwLKfzNOzJFHf0cWp6HjJSIoOxo6Ko6qi3fB0lcT604jq+rczPud2N37ZFYBSkuCAIi39BHSFmcDWfmM8Pc1dE6IVcoNen/fgCKFkX83y9Pf0KNdQy6mpY4lDXZKGTxYnUrOS7nkb+pJVHd+MaWlnHr78qgCJgX99TCvQ4phyms7w7HtHPDZxxQ5cgYnkJeGn8REawaM/dRlYQMhVIyoBOBK3vseoV1eHOxFSJ4Ed+JzPVwot19H6bL2wLCJ6FjtkqNSVL2kIsle/pcZcR3PMsdZB2hZAMXCuzNo8Vl1IxJ+Y9w5ELn+w4aR7wKgqkkvJsTBjjMx8So+cYigj/axgW/fOdVeiBoVrAeaFtUt0xKQnzcbMQlrGVmRSFU09Wvl6mHKAj9JymveOe+wcz0LDiCJs9sPrEc+9bQ63mXz6aFY4EJXuf2QB4BYlwaqYv7GakldpH2 x-ms-exchange-transport-forked: True Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 243f5cd7-2b1a-4431-c64d-08d7fd304a2a X-MS-Exchange-CrossTenant-originalarrivaltime: 21 May 2020 02:40:14.0149 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: yHgItj8I4KTYTYCxYC+4IHrdhFN0v478Vf97MPrbbZ5Qa+9NWTB8oEZYgQPBCsBaTdz1Z1E5Z2VMFJRpDELk0A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR0402MB3461 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Jakub Kicinski Sent: Thursday, May 21, 2020 12:54 A= M > On Wed, 20 May 2020 16:31:53 +0800 fugang.duan@nxp.com wrote: > > From: Fugang Duan > > > > The commit da722186f654(net: fec: set GPR bit on suspend by DT > > configuration) set the GPR reigster offset and bit in driver for wake > > on lan feature. > > > > But it introduces two issues here: > > - one SOC has two instances, they have different bit > > - different SOCs may have different offset and bit > > > > So to support wake-on-lan feature on other i.MX platforms, it should > > configure the GPR reigster offset and bit from DT. > > > > Fixes: da722186f654(net: fec: set GPR bit on suspend by DT > > configuration) > > Signed-off-by: Fugang Duan >=20 > Fixes tag: Fixes: da722186f654(net: fec: set GPR bit on suspend by DT > configuration) Has these problem(s): > - missing space between the SHA1 and the subject Thanks, I will update it v2.