From: Florian Fainelli <f.fainelli@gmail.com>
To: Ben Hutchings <ben@decadent.org.uk>
Cc: Matthew Garrett <matthew.garrett@nebula.com>,
netdev <netdev@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>
Subject: Re: [PATCH V3] net/dt: Add support for overriding phy configuration from device tree
Date: Tue, 4 Feb 2014 14:48:15 -0800 [thread overview]
Message-ID: <CAGVrzcbwiVCj0oETXms6ek+QG13BEbgydLzUEckuGFOhSx0iXQ@mail.gmail.com> (raw)
In-Reply-To: <1391550040.3003.28.camel@deadeye.wl.decadent.org.uk>
2014-02-04 Ben Hutchings <ben@decadent.org.uk>:
> On Tue, 2014-02-04 at 12:39 -0800, Florian Fainelli wrote:
>> 2014-01-17 Matthew Garrett <matthew.garrett@nebula.com>:
>> > Some hardware may be broken in interesting and board-specific ways, such
>> > that various bits of functionality don't work. This patch provides a
>> > mechanism for overriding mii registers during init based on the contents of
>> > the device tree data, allowing board-specific fixups without having to
>> > pollute generic code.
>>
>> It would be good to explain exactly how your hardware is broken
>> exactly. I really do not think that such a fine-grained setting where
>> you could disable, e.g: 100BaseT_Full, but allow 100BaseT_Half to
>> remain usable makes that much sense. In general, Gigabit might be
>> badly broken, but 100 and 10Mbits/sec should work fine. How about the
>> MASTER-SLAVE bit, is overriding it really required?
>
> Yes, it is entirely possible that one or other of the clock modes
> (locally generated vs recovered) is not reliable.
That one is not covered in the existing Ethernet PHY binding, okay for
handling it.
>
>> Is not a PHY fixup registered for a specific OUI the solution you are
>> looking for?
> [...]
>
> The fault is in the board, not the PHY.
What kind of fault at the board level are we talking about? Lack of
specific twisted pair wiring to the RJ-45 jack? Out of spec RXC/TXC on
a (R)GMII path? If the latter, this is going to be via vendor-specific
MII registers, and should be a good enough reason for registering a
PHY fixup. What about pad control, and Ethernet MACs specicif register
affecting the internal delays and such?
--
Florian
next prev parent reply other threads:[~2014-02-04 22:48 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-15 21:38 [PATCH] net/dt: Add support for overriding phy configuration from device tree Matthew Garrett
2014-01-16 13:59 ` Gerhard Sittig
2014-01-16 14:40 ` Matthew Garrett
[not found] ` <20140116135905.GV20094-kDjWylLy9wD0K7fsECOQyeGNnDKD8DIp@public.gmane.org>
2014-01-16 14:47 ` [PATCH V2] " Matthew Garrett
[not found] ` <1389883631-1480-1-git-send-email-matthew.garrett-05XSO3Yj/JvQT0dZR+AlfA@public.gmane.org>
2014-01-16 15:16 ` Arnd Bergmann
[not found] ` < 1389999459-9483-1-git-send-email-matthew.garrett@nebula.com>
2014-01-17 22:57 ` [PATCH V3] " Matthew Garrett
2014-01-19 15:34 ` Ben Hutchings
[not found] ` <1390145654.16433.102.camel-nDn/Rdv9kqW9Jme8/bJn5UCKIB8iOfG2tUK59QYPAWc@public.gmane.org>
2014-02-04 19:01 ` Florian Fainelli
2014-02-04 17:15 ` Grant Likely
2014-02-04 20:39 ` Florian Fainelli
2014-02-04 21:40 ` Ben Hutchings
2014-02-04 22:48 ` Florian Fainelli [this message]
2014-02-05 9:47 ` Grant Likely
2014-02-05 9:51 ` David Laight
[not found] ` <063D6719AE5E284EB5DD2968C1650D6D0F6B8BCA-VkEWCZq2GCInGFn1LkZF6NBPR1lH4CV8@public.gmane.org>
2014-02-07 22:43 ` Florian Fainelli
2014-02-10 16:14 ` Gerlando Falauto
[not found] ` <52F8FB03.6040606-SkAbAL50j+5BDgjK7y7TUQ@public.gmane.org>
2014-02-10 17:09 ` Florian Fainelli
2014-02-11 9:09 ` Gerlando Falauto
[not found] ` <52F9E8E6.1090006-SkAbAL50j+5BDgjK7y7TUQ@public.gmane.org>
2014-02-11 17:43 ` Florian Fainelli
2014-02-12 8:57 ` Gerlando Falauto
2014-07-10 12:37 ` Gerlando Falauto
[not found] ` <53BE8912.4090804-SkAbAL50j+5BDgjK7y7TUQ@public.gmane.org>
2014-07-22 23:40 ` Florian Fainelli
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