From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B348C4360F for ; Wed, 27 Feb 2019 10:16:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 21B4020661 for ; Wed, 27 Feb 2019 10:16:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="kViykZsx" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729163AbfB0KQZ (ORCPT ); Wed, 27 Feb 2019 05:16:25 -0500 Received: from mail-io1-f67.google.com ([209.85.166.67]:45640 "EHLO mail-io1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726062AbfB0KQZ (ORCPT ); Wed, 27 Feb 2019 05:16:25 -0500 Received: by mail-io1-f67.google.com with SMTP id x9so13033187iog.12 for ; Wed, 27 Feb 2019 02:16:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=PSEnQlO4ryJ5lj1eUjpEnJNgdDcKb7s4xmHWDAD6wFA=; b=kViykZsxAUrFfq+Zejo7w/E/rf9vjyhY37z3ZMXmnrLLe+2bIJAcGuMwJ1ykxz9SbX 7Onuzn+mjyJ+CORMNaLMs6rvT1d+wofFxEzhfLwUZN0gYADKSuslU4XizGqvW6cFg8df 9FnZayk+IY23PEAwkPp/yLJHp+V4tlzGmJpS9mk3fGnYY8hXccOJFheQU/A0nK9MOW4p 2NNZxGmcRRGobB4eLftBGlBjbuvCgPNjEdAXyZQwBpJtwHYgXJ743qH03WcsLknv7RxM X2tGkThjD3HG8CmkwnWxElob6zXzjxj1ZPPPiAQSu+zUYB4cPNQCa2Cl1ywz3/pPDzWF 1/Xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=PSEnQlO4ryJ5lj1eUjpEnJNgdDcKb7s4xmHWDAD6wFA=; b=G1ekqmTDFr+4dla5L7Alw2DK+CZVA1msGua6SCBzZvFPVNH3XhtNy+3890x6fw5EuH nTqwlb/LhzVYFfv1e3iHpa4U15NIJ9Y8ZdpE+6F6FGT7k5Bd1LDKbdMIEEdXPm1GBzPQ KWJkH+384N4j+UxnMJBGDr2u6n3T8GEiblnU33gCzkfgqP5A+ML5rdFqEXRkLApDnyYl WFfWLoSIpfuqpIOZqPZ2SdGGWteZK+UEhu8noFH9zS08kxgI6vzW9+ZymsrXdKkKS8Lu zDmyfSPBcenr7Itl2TDgJA0FeGQnRa/xqqnnRn5ATnnaEFKKcwPGc0ph+/bA0uRRGv5O QCwQ== X-Gm-Message-State: APjAAAVJtH+nFcUQceLs3HA3mtm8Ptxlb+gWmfvJoo2lDmAtwhwobFto NaKsnCZbt2EA7b66vLA3FP2cI+pZO8O4lAwVKwZk0g== X-Google-Smtp-Source: APXvYqxO9HQ9KWZQWEqmdGEwKaw5+KXyYiq9o9hgt1i/4kSVEQkCmMwNZAPJ/7nG39ptRqsCkOpqcQLOfsuy1y978mo= X-Received: by 2002:a6b:7b02:: with SMTP id l2mr1605643iop.60.1551262583854; Wed, 27 Feb 2019 02:16:23 -0800 (PST) MIME-Version: 1.0 References: <20190224140426.3267-1-marc.zyngier@arm.com> <20190226232822.GA174696@google.com> In-Reply-To: From: Ard Biesheuvel Date: Wed, 27 Feb 2019 11:16:12 +0100 Message-ID: Subject: Re: [PATCH 0/4] mwifiex PCI/wake-up interrupt fixes To: Marc Zyngier Cc: Brian Norris , Ganapathi Bhat , Jeffy Chen , Heiko Stuebner , Devicetree List , Xinming Hu , "" , linux-pm , "" , Linux Kernel Mailing List , Amitkumar Karwar , linux-rockchip@lists.infradead.org, Nishant Sarmukadam , Rob Herring , "Rafael J. Wysocki" , linux-arm-kernel , Enric Balletbo i Serra , Lorenzo Pieralisi , "David S. Miller" , Kalle Valo , Tony Lindgren Content-Type: text/plain; charset="UTF-8" Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Wed, 27 Feb 2019 at 11:02, Marc Zyngier wrote: > > + Lorenzo > > Hi Brian, > > On 26/02/2019 23:28, Brian Norris wrote: > > + others > > > > Hi Marc, > > > > Thanks for the series. I have a few bits of history to add to this, and > > some comments. > > > > On Sun, Feb 24, 2019 at 02:04:22PM +0000, Marc Zyngier wrote: > >> For quite some time, I wondered why the PCI mwifiex device built in my > >> Chromebook was unable to use the good old legacy interrupts. But as MSIs > >> were working fine, I never really bothered investigating. I finally had a > >> look, and the result isn't very pretty. > >> > >> On this machine (rk3399-based kevin), the wake-up interrupt is described as > >> such: > >> > >> &pci_rootport { > >> mvl_wifi: wifi@0,0 { > >> compatible = "pci1b4b,2b42"; > >> reg = <0x83010000 0x0 0x00000000 0x0 0x00100000 > >> 0x83010000 0x0 0x00100000 0x0 0x00100000>; > >> interrupt-parent = <&gpio0>; > >> interrupts = <8 IRQ_TYPE_LEVEL_LOW>; > >> pinctrl-names = "default"; > >> pinctrl-0 = <&wlan_host_wake_l>; > >> wakeup-source; > >> }; > >> }; > >> > >> Note how the interrupt is part of the properties directly attached to the > >> PCI node. And yet, this interrupt has nothing to do with a PCI legacy > >> interrupt, as it is attached to the wake-up widget that bypasses the PCIe RC > >> altogether (Yay for the broken design!). This is in total violation of the > >> IEEE Std 1275-1994 spec[1], which clearly documents that such interrupt > >> specifiers describe the PCI device interrupts, and must obey the > >> INT-{A,B,C,D} mapping. Oops! > > > > You're not the first person to notice this. All the motivations are not > > necessarily painted clearly in their cover letter, but here are some > > previous attempts at solving this problem: > > > > [RFC PATCH v11 0/5] PCI: rockchip: Move PCIe WAKE# handling into pci core > > https://lkml.kernel.org/lkml/20171225114742.18920-1-jeffy.chen@rock-chips.com/ > > http://lkml.kernel.org/lkml/20171226023646.17722-1-jeffy.chen@rock-chips.com/ > > > > As you can see by the 12th iteration, it wasn't left unsolved for lack > > of trying... > > I wasn't aware of this. That's definitely a better approach than my > hack, and I would really like this to be revived. > I don't think this approach is entirely sound either. >From the side of the PCI device, WAKE# is just a GPIO line, and how it is wired into the system is an entirely separate matter. So I don't think it is justified to overload the notion of legacy interrupts with some other pin that may behave in a way that is vaguely similar to how a true wake-up capable interrupt works. So I'd argue that we should add an optional 'wake-gpio' DT property instead to the generic PCI device binding, and leave the interrupt binding and discovery alone.