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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CH2PR12MB3895.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6d0be91c-c204-467c-4142-08d960fdae19 X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Aug 2021 21:34:51.2399 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: RrzNz+/yqdsmjwECSp2u4R2wZGLS5yPU5T6BjwUdtv+jnX5COBlUqaIS+Pm+B6oZ8FrxeIBx+WS42gCSUFsCSg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB3781 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Hi Andy, Thanks for your help! Please see my comments/questions below. -----Original Message----- From: Andy Shevchenko =20 Sent: Monday, August 16, 2021 8:00 AM To: Andy Shevchenko ; David Thompson ; linux-kernel@vger.kernel.org; linux-gpio@vger.kernel= .org; netdev@vger.kernel.org; linux-acpi@vger.kernel.org Cc: Linus Walleij ; Bartosz Golaszewski ; David S. Miller ; Jakub Kicinski <= kuba@kernel.org>; Rafael J. Wysocki ; Asmaa Mnebhi ; Liming Sun Subject: [PATCH v1 5/6] TODO: gpio: mlxbf2: Introduce IRQ support Importance: High TBD Signed-off-by: Andy Shevchenko --- drivers/gpio/gpio-mlxbf2.c | 106 +++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/drivers/gpio/gpio-mlxbf2.c b/drivers/gpio/gpio-mlxbf2.c index = 3ed95e958c17..bd4c29120b62 100644 --- a/drivers/gpio/gpio-mlxbf2.c +++ b/drivers/gpio/gpio-mlxbf2.c @@ -43,9 +43,13 @@ #define YU_GPIO_MODE0 0x0c #define YU_GPIO_DATASET 0x14 #define YU_GPIO_DATACLEAR 0x18 +#define YU_GPIO_CAUSE_FALL_EN 0x48 #define YU_GPIO_MODE1_CLEAR 0x50 #define YU_GPIO_MODE0_SET 0x54 #define YU_GPIO_MODE0_CLEAR 0x58 +#define YU_GPIO_CAUSE_OR_CAUSE_EVTEN0 0x80 +#define YU_GPIO_CAUSE_OR_EVTEN0 0x94 +#define YU_GPIO_CAUSE_OR_CLRCAUSE 0x98 =20 struct mlxbf2_gpio_context_save_regs { u32 gpio_mode0; @@ -218,6 +222,108 @@ static int mlxbf2_gpio_direction_output(struct gpio_c= hip *chip, return ret; } =20 +static void mlxbf2_gpio_irq_enable(struct mlxbf2_gpio_context *gs, int=20 +offset) { + unsigned long flags; + u32 val; + + spin_lock_irqsave(&gs->gc.bgpio_lock, flags); + val =3D readl(gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE); + val |=3D BIT(offset); + writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE); + + /* The INT_N interrupt level is active low. + * So enable cause fall bit to detect when GPIO + * state goes low. + */ + val =3D readl(gs->gpio_io + YU_GPIO_CAUSE_FALL_EN); + val |=3D BIT(offset); + writel(val, gs->gpio_io + YU_GPIO_CAUSE_FALL_EN); + + /* Enable PHY interrupt by setting the priority level */ + val =3D readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); + val |=3D BIT(offset); + writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); + spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); } + +static void mlxbf2_gpio_irq_disable(struct mlxbf2_gpio_context *gs, int=20 +offset) { + unsigned long flags; + u32 val; + + spin_lock_irqsave(&gs->gc.bgpio_lock, flags); + val =3D readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); + val &=3D ~BIT(offset); + writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); + spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); } + +static void mlxbf2_gpio_irq_ack(struct mlxbf2_gpio_context *gs, int=20 +offset) { + unsigned long flags; + u32 val; + + spin_lock_irqsave(&gs->gc.bgpio_lock, flags); + val =3D readl(gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE); + val |=3D BIT(offset); + writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE); + spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); } + +static irqreturn_t mlxbf2_gpio_irq_handler(int irq, void *ptr) { So how do you suggest registering this handler? 1) should I still use BF_RSH0_DEVICE_YU_INT shared interrupt signal? 2) or does Linux kernel know (based on parsing GpioInt) how trigger the han= dler based on the GPIO datain changing (active low/high)? In this case, the= kernel will call this handler whenever the GPIO pin (9 or 12) value change= s. I need to check whether GPIO is active low/high but lets assume for now = it is open drain active low. We will use acpi_dev_gpio_irq_get to translate= GpioInt to a Linux IRQ number: irq =3D acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), " phy-gpios ", 0); ret =3D devm_request_irq(dev, irq, mlxbf2_gpio_irq_handler, IRQF_ONESHOT | = IRQF_SHARED, dev_name(dev), gs); And I will need to add GpioInt to the GPI0 ACPI table as follows: // GPIO Controller Device(GPI0) { Name(_HID, "MLNXBF22") Name(_UID, Zero) Name(_CCA, 1) Name(_CRS, ResourceTemplate() { // for gpio[0] yu block Memory32Fixed(ReadWrite, 0x0280c000, 0x00000100) GpioInt (Level, ActiveLow, Exclusive, PullDefault, , " \\_SB.GPI0"= ) {9} }) Name(_DSD, Package() { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package() { Package () { "phy-gpios", Package() {^GPI0, 0, 0, 0 }}, Package () { "rst-pin", 32 }, // GPIO pin triggering soft reset= on BlueSphere and PRIS } }) } + struct mlxbf2_gpio_context *gs =3D ptr; + struct gpio_chip *gc =3D &gs->gc; + unsigned long pending; + u32 level; + + pending =3D readl(gs->gpio_io + YU_GPIO_CAUSE_OR_CAUSE_EVTEN0); + for_each_set_bit(level, &pending, gc->ngpio) { + int nested_irq =3D irq_find_mapping(gc->irq.domain, level); + + handle_nested_irq(nested_irq); Now how can the mlxbf_gige_main.c driver also retrieve this nested_irq to r= egister its interrupt handler as well? This irq.domain is only visible to t= he gpio-mlxbf2.c driver isn't it? phydev->irq (below) should be populated with nested_irq at init time becaus= e it is used to register the phy interrupt in this generic function: void phy_request_interrupt(struct phy_device *phydev) { int err; err =3D request_threaded_irq(phydev->irq, NULL, phy_interrupt, IRQF_ONESHOT | IRQF_SHARED, phydev_name(phydev), phydev); if (err) { phydev_warn(phydev, "Error %d requesting IRQ %d, falling back to polling\= n", err, phydev->irq); phydev->irq =3D PHY_POLL; } else { if (phy_enable_interrupts(phydev)) { phydev_warn(phydev, "Can't enable interrupt, falling back to polling\n")= ; phy_free_interrupt(phydev); phydev->irq =3D PHY_POLL; } } } EXPORT_SYMBOL(phy_request_interrupt); + } + + return IRQ_RETVAL(pending); +} + +static void mlxbf2_gpio_irq_mask(struct irq_data *irqd) { + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(irqd); + struct mlxbf2_gpio_context *gs =3D gpiochip_get_data(gc); + int offset =3D irqd_to_hwirq(irqd) % MLXBF2_GPIO_MAX_PINS_PER_BLOCK; Why is the modulo needed? Isn't the hwirq returned a number between 0 and M= LXBF2_GPIO_MAX_PINS_PER_BLOCK-1 ? + + mlxbf2_gpio_irq_disable(gs, offset); +} + +static void mlxbf2_gpio_irq_unmask(struct irq_data *irqd) { + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(irqd); + struct mlxbf2_gpio_context *gs =3D gpiochip_get_data(gc); + int offset =3D irqd_to_hwirq(irqd) % MLXBF2_GPIO_MAX_PINS_PER_BLOCK; + + mlxbf2_gpio_irq_enable(gs, offset); +} + +static void mlxbf2_gpio_irq_bus_lock(struct irq_data *irqd) { + mutex_lock(yu_arm_gpio_lock_param.lock); +} + +static void mlxbf2_gpio_irq_bus_sync_unlock(struct irq_data *irqd) { + mutex_unlock(yu_arm_gpio_lock_param.lock); +} + +static struct irq_chip mlxbf2_gpio_irq_chip =3D { + .name =3D "mlxbf2_gpio", + .irq_mask =3D mlxbf2_gpio_irq_mask, + .irq_unmask =3D mlxbf2_gpio_irq_unmask, + .irq_bus_lock =3D mlxbf2_gpio_irq_bus_lock, + .irq_bus_sync_unlock =3D mlxbf2_gpio_irq_bus_sync_unlock, +}; + We also need to make sure that the gpio driver is loaded before the mlxbf-g= ige driver. Otherwise, the mlxbf-gige 1G interface fails to come up. I have= implemented this dependency on the gpio driver before, something like this= at the end of the mlxbf-gige driver: MODULE_SOFTDEP("pre: gpio_mlxbf2"); /* BlueField-2 GPIO driver initialization routine. */ static int mlxbf2_= gpio_probe(struct platform_device *pdev) -- 2.30.2