From: "Badel, Laurent" <LaurentBadel@eaton.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: Marco Felsch <m.felsch@pengutronix.de>,
"davem@davemloft.net" <davem@davemloft.net>,
"fugang.duan@nxp.com" <fugang.duan@nxp.com>,
"kuba@kernel.org" <kuba@kernel.org>,
Heiner Kallweit <hkallweit1@gmail.com>,
"linux@armlinux.org.uk" <linux@armlinux.org.uk>,
"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
"lgirdwood@gmail.com" <lgirdwood@gmail.com>,
"broonie@kernel.org" <broonie@kernel.org>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"richard.leitner@skidata.com" <richard.leitner@skidata.com>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"f.fainelli@gmail.com" <f.fainelli@gmail.com>,
"Quette, Arnaud" <ArnaudQuette@Eaton.com>
Subject: RE: [EXTERNAL] Re: [PATCH net 0/4] Restore and fix PHY reset for SMSC LAN8720
Date: Wed, 4 Nov 2020 13:14:06 +0000 [thread overview]
Message-ID: <CY4PR1701MB1878601405CDE35CBFB0EA52DFEF0@CY4PR1701MB1878.namprd17.prod.outlook.com> (raw)
In-Reply-To: <20201104131104.GV933237@lunn.ch>
>
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-----Original Message-----
> From: Andrew Lunn <andrew@lunn.ch>
> Sent: Wednesday, November 04, 2020 2:11 PM
> To: Badel, Laurent <LaurentBadel@eaton.com>
> Cc: Marco Felsch <m.felsch@pengutronix.de>; davem@davemloft.net;
> fugang.duan@nxp.com; kuba@kernel.org; Heiner Kallweit
> <hkallweit1@gmail.com>; linux@armlinux.org.uk; p.zabel@pengutronix.de;
> lgirdwood@gmail.com; broonie@kernel.org; robh+dt@kernel.org;
> richard.leitner@skidata.com; netdev@vger.kernel.org;
> devicetree@vger.kernel.org; f.fainelli@gmail.com; Quette, Arnaud
> <ArnaudQuette@Eaton.com>
> Subject: Re: [EXTERNAL] Re: [PATCH net 0/4] Restore and fix PHY reset for
> SMSC LAN8720
>
> > > > (ii) This defeats the purpose of a previous commit [2] that
> > > > disabled the ref clock for power saving reasons. If a ref clock
> > > > for the PHY is specified in DT, the SMSC driver will keep it
> > > > always on (confirmed with scope).
> > >
> > > NACK, the clock provider can be any clock. This has nothing to do
> > > with the FEC clocks. The FEC _can_ be used as clock provider.
> >
> > I'm sure you understand this much better than I do. What I can say is
> > that I directly measured the ref clk and found that when I add the
> > clock to the DT the clock stays on forever. Basically it seems like
> > the FEC calls to
> > clk_disable_unprepare() don't work in this case, though I'm not sure
> > about the reason behind this.
>
> The reason is easy to explain. The clock API is reference counted. It counts
> how many times a clock is turned on and off. A clock has to be turned off as
> many times as it was turned on before the hardware actually turns off. So
> you have the FEC turning the clock on during probe, followed by the phy
> turning the clock on. Some time later the FEC turns the clock off for run time
> power saving, but there is still one reference to the clock held by the PHY, so
> the hardware is left ticking.
>
> Andrew
That makes a lot of sense, thanks very much for the explanation.
prev parent reply other threads:[~2020-11-04 13:14 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-27 23:25 [PATCH net 0/4] Restore and fix PHY reset for SMSC LAN8720 Badel, Laurent
2020-10-28 23:10 ` Jakub Kicinski
2020-11-02 15:24 ` [EXTERNAL] " Badel, Laurent
2020-10-29 8:16 ` Marco Felsch
2020-11-04 12:08 ` [EXTERNAL] " Badel, Laurent
2020-11-04 13:11 ` Andrew Lunn
2020-11-04 13:14 ` Badel, Laurent [this message]
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