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Tue, 27 Oct 2020 23:25:01 +0000 From: "Badel, Laurent" To: "davem@davemloft.net" , "m.felsch@pengutronix.de" , "fugang.duan@nxp.com" , "kuba@kernel.org" , "andrew@lunn.ch" , Heiner Kallweit , "linux@armlinux.org.uk" , "p.zabel@pengutronix.de" , "lgirdwood@gmail.com" , "broonie@kernel.org" , "robh+dt@kernel.org" , "richard.leitner@skidata.com" , "netdev@vger.kernel.org" , "devicetree@vger.kernel.org" , "f.fainelli@gmail.com" CC: "Quette, Arnaud" Subject: [PATCH net 0/4] Restore and fix PHY reset for SMSC LAN8720 Thread-Topic: [PATCH net 0/4] Restore and fix PHY reset for SMSC LAN8720 Thread-Index: AdasuCyaTCUfPNScQDqUis8Tkf1v8A== Date: Tue, 27 Oct 2020 23:25:01 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: davemloft.net; dkim=none (message not signed) header.d=none;davemloft.net; dmarc=none action=none header.from=eaton.com; x-originating-ip: [89.217.230.232] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 32b8073d-96ff-44cd-63a6-08d87acf872f x-ms-traffictypediagnostic: CY4PR17MB1256: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CY4PR1701MB1878.namprd17.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 32b8073d-96ff-44cd-63a6-08d87acf872f X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Oct 2020 23:25:01.6574 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d6525c95-b906-431a-b926-e9b51ba43cc4 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 5fRWcdUv83mq/zK3FtmSahKfiF2oU4aCjCvc2agy6YXgYJQiYnWhzvSdDPBgyvgIWMswwpyNwV9YdoQtAVDGaw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR17MB1256 X-TM-SNTS-SMTP: B372A1CFC4CD810F7035AB574B1648659B6AD0B14BA34484A9DC680389DED7BA2002:8 X-OriginatorOrg: eaton.com X-EXCLAIMER-MD-CONFIG: 96b59d02-bc1a-4a40-8c96-611cac62bce9 X-TM-AS-GCONF: 00 X-TM-AS-Product-Ver: IMSVA-9.1.0.1988-8.6.0.1013-25752.003 X-TM-AS-Result: No--1.742-10.0-31-10 X-imss-scan-details: No--1.742-10.0-31-10 X-TMASE-Version: IMSVA-9.1.0.1988-8.6.1013-25752.003 X-TMASE-Result: 10--1.741800-10.000000 X-TMASE-MatchedRID: BhcknCqDkQeYizZS4XBb35VRzPxemJL0APiR4btCEeYd0WOKRkwsh4JV W4oTDi/+jmvHbETf1n9nAwKLgKVGAEP8wYcu6bTegq+cWtkrZSExXH/dlhvLv8AkyHiYDAQbaGR LCnKSipX+/nPGlAmfKbFmZolQJCqvTpAZ21pPBYGJUlmL3Uj0mPMMVfCUdzaoSgypjNmDEOuyVb 9d3WTXx365wCHja8S0ZJVHNW1Xjrx+7Gr2hULRCp2qrRzrhHWq9fvWztwgm5OpUxQxmTD4QmxzJ LA9fer3qwRdWOjXpsklnCfhOzHZ4CLSA2Bw59G2LTHwnYOikQ0GchEhVwJY34PLx3vY4vNi4tEY aayedIOD8GyWfZ4BMfFEd/KZz2rVlmP4dSOrQfZPs79gcmEg0KKRkGOW2z9yHNJ22Gj+T8PD9iR j9LIMxiijdXEGp4FgxIlmjVV6USrf553KJlUviG6HurDH4PpPMC4zO7d4kaOBTfzBFuc88sbQuY gvFFjzOelg+pLqPPEnayvpxBMhhFGEd5OSBmbm2oIkXC6Ol0DyRrv+hwfKX3+liOD53f81+gtHj 7OwNO19R4Ss0oUmJ8R2sbRjZp+3JoF2rcutTrhHbKsQEaUG1edmGT3Unrl0mdWfOAUbGFx1hBEr p3pG/UY/vonnIqoPhOEijvod03bfO1l1W46FFU8jxvONzeaafEwSr4v8H0fxemJbhO7ZfZTIXce rO/Bu X-TMASE-SNAP-Result: 1.821001.0001-0-1-12:0,22:0,33:0,34:0-0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org =EF=BB=BFSubject: [PATCH net 0/4] Restore and fix PHY reset for SMSC LAN872= 0 Description: A recent patchset [1] added support in the SMSC PHY driver for managing the ref clock and therefore removed the PHY_RST_AFTER_CLK_EN flag for the LAN8720 chip. The ref clock is passed to the SMSC driver through a new property "clocks" in the device tree. There appears to be two potential caveats: (i) Building kernel 5.9 without updating the DT with the "clocks" property for SMSC PHY, would break systems previously relying on the PHY reset workaround (SMSC driver cannot grab the ref clock, so it is still managed by FEC, but the PHY is not reset because PHY_RST_AFTER_CLK_EN is not set). This may lead to occasional loss of ethernet connectivity in these systems, that is difficult to debug. (ii) This defeats the purpose of a previous commit [2] that disabled the ref clock for power saving reasons. If a ref clock for the PHY is specified in DT, the SMSC driver will keep it always on (confirmed with=20 scope). While this removes the need for additional PHY resets (only a=20 single reset is needed after power up), this prevents the FEC from saving power by disabling the refclk. Since there may be use cases where one is interested in saving power, keep this option available when no ref clock is specified for the PHY, by fixing issues with the PHY reset. Main changes proposed to address this: (a) Restore PHY_RST_AFTER_CLK_EN for LAN8720, but explicitly clear it if the SMSC driver succeeds in retrieving the ref clock. (b) Fix phy_reset_after_clk_enable() to work in interrupt mode, by re-configuring the PHY registers after reset. Tests: against net tree 5.9, including allyes/no/modconfig. 10 pieces of an iMX28-EVK-based board were tested, 3 of which were found to exhibit issues when the "clocks" property was left unset. Issues were fixed by the present patchset. References: [1] commit d65af21842f8 ("net: phy: smsc: LAN8710/20: remove PHY_RST_AFTER_CLK_EN flag") commit bedd8d78aba3 ("net: phy: smsc: LAN8710/20: add phy refclk in support") [2] commit e8fcfcd5684a ("net: fec: optimize the clock management to save power") Laurent Badel (5): net:phy:smsc: enable PHY_RST_AFTER_CLK_EN if ref clock is not set net:phy:smsc: expand documentation of clocks property net:phy: add phy_device_reset_status() support net:phy: fix phy_reset_after_clk_enable() net:phy: add SMSC PHY reset on PM restore .../devicetree/bindings/net/smsc-lan87xx.txt | 3 +- drivers/net/phy/mdio_device.c | 18 +++++++++++ drivers/net/phy/phy_device.c | 32 +++++++++++++++---- drivers/net/phy/smsc.c | 5 ++- include/linux/mdio.h | 1 + include/linux/phy.h | 5 +++ 6 files changed, 55 insertions(+), 9 deletions(-) --=20 2.17.1 ----------------------------- Eaton Industries Manufacturing GmbH ~ Registered place of business: Route d= e la Longeraie 7, 1110, Morges, Switzerland=20 -----------------------------