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Fri, 9 Dec 2022 00:56:47 +0000 Received: from DM6PR11MB4657.namprd11.prod.outlook.com ([fe80::5006:f262:3103:f080]) by DM6PR11MB4657.namprd11.prod.outlook.com ([fe80::5006:f262:3103:f080%7]) with mapi id 15.20.5880.014; Fri, 9 Dec 2022 00:56:47 +0000 From: "Kubalewski, Arkadiusz" To: Jakub Kicinski , Jiri Pirko CC: "netdev.dump@gmail.com" , 'Vadim Fedorenko' , 'Jonathan Lemon' , "'Paolo Abeni'" , "netdev@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-clk@vger.kernel.org" Subject: RE: [RFC PATCH v4 0/4] Create common DPLL/clock configuration API Thread-Topic: [RFC PATCH v4 0/4] Create common DPLL/clock configuration API Thread-Index: AQHZBDr1K1GsCJct2UayQH1vPDEq/65XZyGAgAMK4oCAAFcrAIAG+ucAgAC+YICAAJp7gIAAyxiAgADc/oCAAAQyUA== Date: Fri, 9 Dec 2022 00:56:47 +0000 Message-ID: References: <20221129213724.10119-1-vfedorenko@novek.ru> <20221206184740.28cb7627@kernel.org> <10bb01d90a45$77189060$6549b120$@gmail.com> <20221207152157.6185b52b@kernel.org> <20221208163949.3833fe7b@kernel.org> In-Reply-To: <20221208163949.3833fe7b@kernel.org> Accept-Language: pl-PL, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR11MB4657.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 19be3b91-5306-4bbd-9fff-08dad9803faa X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Dec 2022 00:56:47.2895 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: fpNZ+8HrX6tzcE9/Cbgtk+gODsS9CuKNlXOKBy/naRJm+ejZg2d+pgkuiU4CgA0RhaqNZyEWCzYnqKO15FU6dKf6fV99I7c/AWxh8/fvags= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4520 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org >From: Jakub Kicinski >Sent: Friday, December 9, 2022 1:40 AM >On Thu, 8 Dec 2022 12:28:51 +0100 Jiri Pirko wrote: >> >I think we discussed using serial numbers. >> >> Can you remind it? Do you mean serial number of pin? > >Serial number of the ASIC, board or device. >Something will have a serno, append to that your pin id of choice - et >voila! Right now, driver can find dpll with: struct dpll_device *dpll_device_get_by_cookie(u8 cookie[DPLL_COOKIE_LEN], enum dpll_type type, u8 idx);= =20 Where arguments would be the same as given when first instance have allocat= ed dpll with: struct dpll_device *dpll_device_alloc(struct dpll_device_ops *ops, enum dpll_type type, const u8 cookie[DPLL_COOKIE_LEN], u8 dev_driver_idx, void *priv, struct device *parent); Which means all driver instances must know those values if they need to sha= re dpll or pins. Thanks, Arkadiusz > >> >Are you saying within the driver it's somehow easier? The driver >> >state is mostly per bus device, so I don't see how. >> >> You can have some shared data for multiple instances in the driver >> code, why not? > >The question is whether it's easier. >Easier to ensure quality of n implementations in random drivers. >Or one implementation in the core, with a lot of clever people paying >attention and reviewing the code. > >> >> There are many problems with that approach, and the submitted patch >> >> is not explaining any of them. E.g. it contains the >> >> dpll_muxed_pin_register but no free counterpart + no flows. >> > >> >SMOC. >> >> Care to spell this out. I guess you didn't mean "South Middlesex >> Opportunity Council" :D > >Simple matter of coding.