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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 17399525-aee7-44a6-827f-08d6fa39411c X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Jun 2019 13:21:53.1111 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: manishc@marvell.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR18MB2892 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-06-26_07:,, signatures=0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org > In msix mode there's no need to explicitly disable completion interrupts,= they > are reliably auto-masked, according to my observations. > I tested this on two QLE8142 adapters. >=20 > Do you have reason to believe this might not always be the case? How did you check auto-masking of MSI-X interrupts ? I was just wondering about the below comment in ql_disable_completion_inter= rupt(), where for MSI-X it does disable completion intr for zeroth intr. Seems special case for zeroth intr in MSI-X particular to this device. /* HW disables for us if we're MSIX multi interrupts and * it's not the default (zeroeth) interrupt. */ if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) return 0;