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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: UdaS8WQBLfCqh6Z1SiWa/jGx8ZJMrQ6IEr5s98ehaucS9LSllZeyx/nV4h2sKpqTQN/xG3h31bmdnWtoUd6KKmjoDLdlBrbD4RUU0tfZ9d8UOl/IVHYygEfLcMi3wWZZ8/c84cRLjQWAOVyiC4dKL3mmfIwlt5E2QWuoHh3T+Q962GMEYxktnGFlqvvpW6xnrDK+Y2OLqgtWWkWfvyLwIPwDd8H+1yXxtFTUlZ/zTkCE7ufdwH6rIC6/k6VkjOBqNPSZJt4JFbd9mUTDPLmAQ6RZudyT0QM3l/6lkifWKlcTceztCI+GSNkHX9J/NnshgK2dfIblUhAkVcYaHlFeHq8MFJia+FBR0CSjZJKv5HVbS1Duq+S/70JbYDYSriGSrDyDwFL5+dJqS906BfrzX6EhqecTyx9xFD/m8zQy9JI= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: b6fe9dd5-f07d-45bb-f7ce-08d725fc3be4 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Aug 2019 05:55:56.2062 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: sa1o5Kitd8N4p466dn8n4XsUTUdDW0zSY8cOHvkcKyqnAgey01uKGmJSsLdZxpXOFCDjNO4on8QWMOcKBRI5RQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0402MB2768 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Andrew Lunn Sent: Tuesday, August 20, 2019 9:04 PM > On Tue, Aug 20, 2019 at 02:32:26AM +0000, Andy Duan wrote: > > From: Andrew Lunn > > > On Mon, Aug 19, 2019 at 05:11:14PM +0000, Marco Hartmann wrote: > > > > As of yet, the Fast Ethernet Controller (FEC) driver only supports > > > > Clause 22 conform MDIO transactions. IEEE 802.3ae Clause 45 > > > > defines a modified MDIO protocol that uses a two staged access > > > > model in order to increase the address space. > > > > > > > > This patch adds support for Clause 45 conform MDIO read and write > > > > operations to the FEC driver. > > > > > > Hi Marco > > > > > > Do all versions of the FEC hardware support C45? Or do we need to > > > make use of the quirk support in this driver to just enable it for so= me > revisions of FEC? > > > > > > Thanks > > > Andrew > > > > i.MX legacy platforms like i.MX6/7 series, they doesn't support Write &= Read > Increment. > > But for i.MX8MQ/MM series, it support C45 full features like Write & Re= ad > Increment. > > > > For the patch itself, it doesn't support Write & Read Increment, so I > > think the patch doesn't need to add quirk support. >=20 > Hi Andy >=20 > So what happens with something older than a i.MX8MQ/MM when a C45 > transfer is attempted? This patch adds a new write. Does that write > immediately trigger a completion interrupt? Does it never trigger an inte= rrupt, > and we have to wait FEC_MII_TIMEOUT? >=20 > Ideally, if the hardware does not support C45, we want it to return > EOPNOTSUPP. >=20 > Thanks > Andrew It still trigger an interrupt to wakeup the completion, we have to wait FEC= _MII_TIMEOUT. Older chips just support part of C45 feature just like the patch implementa= tion.=20