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Date:   Mon, 12 Apr 2021 16:14:23 +0200
From:   Andrew Lunn <andrew@lunn.ch>
To:     Michal =?utf-8?B?Vm9rw6HEjQ==?= <michal.vokac@ysoft.com>
Cc:     Jonathan McDowell <noodles@earth.li>,
        Florian Fainelli <f.fainelli@gmail.com>,
        David Miller <davem@davemloft.net>, netdev@vger.kernel.org
Subject: Re: Broken imx6 to QCA8334 connection since PHYLIB to PHYLINK
 conversion
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> [1] https://elixir.bootlin.com/linux/v5.12-rc7/source/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi#L101


&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rgmii-id";
	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <20>;
	phy-supply = <&sw2_reg>;
	phy-handle = <&ethphy0>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		phy_port2: phy@1 {
			reg = <1>;
		};

		phy_port3: phy@2 {
			reg = <2>;
		};

		switch@10 {
			compatible = "qca,qca8334";
			reg = <10>;

			switch_ports: ports {
				#address-cells = <1>;
				#size-cells = <0>;

				ethphy0: port@0 {
					reg = <0>;
					label = "cpu";
					phy-mode = "rgmii-id";
					ethernet = <&fec>;

					fixed-link {
						speed = <1000>;
						full-duplex;
					};
				};

The fec phy-handle = <&ethphy0>; is pointing to the PHY of switch port
0. This seems wrong. Does the FEC have a PHY? Do you connect the FEC
and the SWITCH at the RGMII level? Or with two back to back PHYs?

If you are doing it RGMII level, the FEC also needs a fixed-link.

    Andrew