From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89D7FC4338F for ; Mon, 9 Aug 2021 13:35:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6D9AB61058 for ; Mon, 9 Aug 2021 13:35:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233420AbhHINfu (ORCPT ); Mon, 9 Aug 2021 09:35:50 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:39978 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229474AbhHINfs (ORCPT ); Mon, 9 Aug 2021 09:35:48 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=4ANahQ2cqmBDHTiQEa5YLbEqQAFRzNMJ3iDCtBOXvgI=; b=ZBYHEpi+HbXPwkc/gBLFF8X5pf 880QW5VjvwWasYI5PzgwK41YsF9fYzv0YeC7r6EwGDR7Au3ztt/yjWgGwM2pvhpBiDrpowKHpPptG OUqP2HB7ie0GOy8N5LlbFHRKbBZ63pc9lDK5Q+a6nscl9Vjemgdz3XQnB/GFs6V7icdE=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1mD5Qr-00Gi51-F9; Mon, 09 Aug 2021 15:35:09 +0200 Date: Mon, 9 Aug 2021 15:35:09 +0200 From: Andrew Lunn To: Wong Vee Khee Cc: Vivien Didelot , Florian Fainelli , "David S . Miller" , Jakub Kicinski , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Heiner Kallweit , Russell King , Voon Weifeng , Michael Sit Wei Hong , Vladimir Oltean , linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH net-next 1/2] net: pcs: xpcs: enable skip xPCS soft reset Message-ID: References: <20210809102229.933748-1-vee.khee.wong@linux.intel.com> <20210809102229.933748-2-vee.khee.wong@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210809102229.933748-2-vee.khee.wong@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Mon, Aug 09, 2021 at 06:22:28PM +0800, Wong Vee Khee wrote: > From: Michael Sit Wei Hong > > Unlike any other platforms, Intel AlderLake-S uses Synopsys SerDes where > all the SerDes PLL configurations are controlled by the xPCS at the BIOS > level. If the driver perform a xPCS soft reset on initialization, these > settings will be switched back to the power on reset values. > > This changes the xpcs_create function to take in an additional argument > to check if the platform request to skip xPCS soft reset during device > initialization. Why not just call into the BIOS and ask it to configure the SERDES? Isn't that what ACPI is all about, hiding the details from the OS? Or did the BIOS writers not add a control method to do this? Andrew