From: Daniel Golle <daniel@makrotopia.org>
To: linux-mediatek@lists.infradead.org, netdev@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: Felix Fietkau <nbd@nbd.name>, John Crispin <john@phrozen.org>,
Sean Wang <sean.wang@mediatek.com>,
Mark Lee <Mark-MC.Lee@mediatek.com>,
"David S. Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Russell King <linux@armlinux.org.uk>,
Andrew Lunn <andrew@lunn.ch>
Subject: [PATCH v6 2/2] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO access
Date: Tue, 28 Dec 2021 00:09:26 +0000 [thread overview]
Message-ID: <YcpVtjykiS7mgtT5@makrotopia.org> (raw)
In-Reply-To: <YcnoAscVe+2YILT8@shell.armlinux.org.uk> <YcnlMtninjjjPhjI@makrotopia.org>
Implement read and write access to IEEE 802.3 Clause 45 Ethernet
phy registers.
Tested on the Ubiquiti UniFi 6 LR access point featuring
MediaTek MT7622BV WiSoC with Aquantia AQR112C.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 56 ++++++++++++++++++---
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 ++
2 files changed, 51 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 72b3ae7b5ff8d..4dc1bb521ed76 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -102,10 +102,30 @@ static int _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg,
write_data &= 0xffff;
- mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
- (phy_reg << PHY_IAC_REG_SHIFT) |
- (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
- MTK_PHY_IAC);
+ if (phy_reg & MII_ADDR_C45) {
+ u8 dev_num = (phy_reg >> MII_DEVADDR_C45_SHIFT) & GENMASK(4, 0);
+ u16 reg = (u16)(phy_reg & MII_REGADDR_C45_MASK);
+
+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_SET_ADDR |
+ (phy_addr << PHY_IAC_ADDR_SHIFT) |
+ (dev_num << PHY_IAC_REG_SHIFT) |
+ reg,
+ MTK_PHY_IAC);
+
+ if (mtk_mdio_busy_wait(eth))
+ return -EBUSY;
+
+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_WRITE |
+ (phy_addr << PHY_IAC_ADDR_SHIFT) |
+ (dev_num << PHY_IAC_REG_SHIFT) |
+ write_data,
+ MTK_PHY_IAC);
+ } else {
+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
+ (phy_reg << PHY_IAC_REG_SHIFT) |
+ (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
+ MTK_PHY_IAC);
+ }
if (mtk_mdio_busy_wait(eth))
return -EBUSY;
@@ -118,10 +138,29 @@ static int _mtk_mdio_read(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg)
if (mtk_mdio_busy_wait(eth))
return -EBUSY;
- mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
- (phy_reg << PHY_IAC_REG_SHIFT) |
- (phy_addr << PHY_IAC_ADDR_SHIFT),
- MTK_PHY_IAC);
+ if (phy_reg & MII_ADDR_C45) {
+ u8 dev_num = (phy_reg >> MII_DEVADDR_C45_SHIFT) & GENMASK(4, 0);
+ u16 reg = (u16)(phy_reg & MII_REGADDR_C45_MASK);
+
+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_SET_ADDR |
+ (phy_addr << PHY_IAC_ADDR_SHIFT) |
+ (dev_num << PHY_IAC_REG_SHIFT) |
+ reg,
+ MTK_PHY_IAC);
+
+ if (mtk_mdio_busy_wait(eth))
+ return -EBUSY;
+
+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_READ_C45 |
+ (phy_addr << PHY_IAC_ADDR_SHIFT) |
+ (dev_num << PHY_IAC_REG_SHIFT),
+ MTK_PHY_IAC);
+ } else {
+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
+ (phy_reg << PHY_IAC_REG_SHIFT) |
+ (phy_addr << PHY_IAC_ADDR_SHIFT),
+ MTK_PHY_IAC);
+ }
if (mtk_mdio_busy_wait(eth))
return -EBUSY;
@@ -493,6 +532,7 @@ static int mtk_mdio_init(struct mtk_eth *eth)
eth->mii_bus->name = "mdio";
eth->mii_bus->read = mtk_mdio_read;
eth->mii_bus->write = mtk_mdio_write;
+ eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
eth->mii_bus->priv = eth;
eth->mii_bus->parent = eth->dev;
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 5ef70dd8b49c6..b73d8adc9d24c 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -341,9 +341,12 @@
/* PHY Indirect Access Control registers */
#define MTK_PHY_IAC 0x10004
#define PHY_IAC_ACCESS BIT(31)
+#define PHY_IAC_SET_ADDR 0
#define PHY_IAC_READ BIT(19)
+#define PHY_IAC_READ_C45 (BIT(18) | BIT(19))
#define PHY_IAC_WRITE BIT(18)
#define PHY_IAC_START BIT(16)
+#define PHY_IAC_START_C45 0
#define PHY_IAC_ADDR_SHIFT 20
#define PHY_IAC_REG_SHIFT 25
#define PHY_IAC_TIMEOUT HZ
--
2.34.1
next prev parent reply other threads:[~2021-12-28 0:09 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-26 21:29 [PATCH] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO access Daniel Golle
2021-12-26 21:51 ` Andrew Lunn
2021-12-26 21:57 ` Russell King (Oracle)
2021-12-26 22:26 ` Andrew Lunn
2021-12-26 23:23 ` [PATCH v2] " Daniel Golle
2021-12-27 16:09 ` [PATCH v3] " Daniel Golle
2021-12-27 16:21 ` Russell King (Oracle)
2021-12-27 17:51 ` [PATCH v4 0/2] net: mtk_soc_eth: " Daniel Golle
2021-12-27 17:51 ` [PATCH v4 1/2] net: mtk_eth_soc: fix return value of MDIO operations Daniel Golle
2021-12-27 17:52 ` [PATCH v4 2/2] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO access Daniel Golle
2021-12-27 18:30 ` [PATCH v5 0/2] " Daniel Golle
2021-12-27 18:31 ` [PATCH v5 1/2] net: ethernet: mtk_eth_soc: fix return value of MDIO ops Daniel Golle
2021-12-27 18:31 ` [PATCH v5 2/2] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO access Daniel Golle
2021-12-28 0:07 ` [PATCH v6 0/2] " Daniel Golle
2021-12-28 0:08 ` [PATCH v6 1/2] net: ethernet: mtk_eth_soc: fix return value of MDIO ops Daniel Golle
2021-12-28 0:09 ` Daniel Golle [this message]
2021-12-28 1:10 ` [PATCH v7 0/2] net: ethernet: mtk_soc_eth: implement Clause 45 MDIO access Daniel Golle
2021-12-28 1:43 ` Jakub Kicinski
2021-12-28 1:10 ` [PATCH v7 1/2] net: ethernet: mtk_eth_soc: fix return value of MDIO ops Daniel Golle
2021-12-28 1:11 ` [PATCH v7 2/2] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO access Daniel Golle
2021-12-28 11:46 ` Russell King (Oracle)
2021-12-28 21:03 ` [PATCH v8 0/3] net: ethernet: mtk_eth_soc: refactoring and Clause 45 Daniel Golle
2021-12-28 21:05 ` [PATCH v8 1/3] net: mdio: add helpers to extract clause 45 regad and devad fields Daniel Golle
2021-12-28 21:05 ` [PATCH v8 2/3] net: ethernet: mtk_eth_soc: fix return value and refactor MDIO ops Daniel Golle
2021-12-28 21:05 ` [PATCH v8 3/3] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO access Daniel Golle
2021-12-31 20:52 ` [PATCH v9 0/3] net: ethernet: mtk_eth_soc: refactoring and Clause 45 Daniel Golle
2021-12-31 20:54 ` [PATCH v9 2/3] net: ethernet: mtk_eth_soc: fix return value and refactor MDIO ops Daniel Golle
2021-12-31 20:54 ` [PATCH v9 3/3] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO access Daniel Golle
2021-12-31 20:57 ` [PATCH v9 1/3] net: mdio: add helpers to extract clause 45 regad and devad fields Daniel Golle
2022-01-01 17:20 ` Andrew Lunn
2022-01-02 15:47 ` [PATCH v10 0/3] net: ethernet: mtk_eth_soc: refactoring and Clause 45 Daniel Golle
2022-01-02 15:51 ` Russell King (Oracle)
2022-01-02 15:48 ` [PATCH v10 1/3] net: ethernet: mtk_eth_soc: fix return value and refactor MDIO ops Daniel Golle
2022-01-02 16:43 ` Andrew Lunn
2022-01-02 15:48 ` [PATCH v10 2/3] net: mdio: add helpers to extract clause 45 regad and devad fields Daniel Golle
2022-01-02 16:44 ` Andrew Lunn
2022-01-02 15:49 ` [PATCH v10 3/3] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO access Daniel Golle
[not found] ` <Yc9tk6IZ0ldqHx4Y@makrotopia.org>
2022-01-01 17:18 ` [PATCH v9 1/3] net: mdio: add helpers to extract clause 45 regad and devad fields Andrew Lunn
2022-01-01 17:41 ` Daniel Golle
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