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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id q63-20020a81b242000000b0054c0c9e4043sm4252004ywh.95.2023.04.12.08.25.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 08:25:38 -0700 (PDT) Date: Wed, 12 Apr 2023 11:25:36 -0400 From: Brian Masney To: Andrew Halaney Cc: linux-kernel@vger.kernel.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, richardcochran@gmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org, echanude@redhat.com, ncai@quicinc.com, jsuraj@qti.qualcomm.com, hisunil@quicinc.com Subject: Re: [PATCH v4 0/3] Add EMAC3 support for sa8540p-ride (devicetree/clk bits) Message-ID: References: <20230411202009.460650-1-ahalaney@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230411202009.460650-1-ahalaney@redhat.com> User-Agent: Mutt/2.2.7 (2022-08-07) Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On Tue, Apr 11, 2023 at 03:20:06PM -0500, Andrew Halaney wrote: > This is a forward port / upstream refactor of code delivered > downstream by Qualcomm over at [0] to enable the DWMAC5 based > implementation called EMAC3 on the sa8540p-ride dev board. > > From what I can tell with the board schematic in hand, > as well as the code delivered, the main changes needed are: > > 1. A new address space layout for dwmac5/EMAC3 MTL/DMA regs > 2. A new programming sequence required for the EMAC3 base platforms > > This series addresses the devicetree and clock changes to support this > hardware bringup. > > As requested[1], it has been split up by compile deps / maintainer tree. > The associated v4 of the netdev specific changes can be found at [2]. > Together, they result in the ethernet controller working for > both controllers on this platform. Looks good to me! Tested-by: Brian Masney