From: Daniel Golle <daniel@makrotopia.org>
To: netdev@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Russell King <linux@armlinux.org.uk>,
Heiner Kallweit <hkallweit1@gmail.com>,
Lorenzo Bianconi <lorenzo@kernel.org>,
Mark Lee <Mark-MC.Lee@mediatek.com>,
John Crispin <john@phrozen.org>, Felix Fietkau <nbd@nbd.name>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
DENG Qingfang <dqfext@gmail.com>,
Landen Chao <Landen.Chao@mediatek.com>,
Sean Wang <sean.wang@mediatek.com>,
Paolo Abeni <pabeni@redhat.com>, Jakub Kicinski <kuba@kernel.org>,
Eric Dumazet <edumazet@google.com>,
"David S. Miller" <davem@davemloft.net>,
Vladimir Oltean <olteanv@gmail.com>,
Florian Fainelli <f.fainelli@gmail.com>,
Andrew Lunn <andrew@lunn.ch>
Cc: "Jianhui Zhao" <zhaojh329@gmail.com>, "Bjørn Mork" <bjorn@mork.no>
Subject: [PATCH 2/9] net: ethernet: mtk_eth_soc: set MDIO bus clock frequency
Date: Fri, 3 Feb 2023 07:01:01 +0000 [thread overview]
Message-ID: <a613b66b4872b5f3f09544138d03d5326a8f6f8b.1675407169.git.daniel@makrotopia.org> (raw)
In-Reply-To: <cover.1675407169.git.daniel@makrotopia.org>
Set MDIO bus clock frequency and allow setting a custom maximum
frequency from device tree.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 25 +++++++++++++++++++++
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 5 +++++
2 files changed, 30 insertions(+)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index a44ffff48c7b..9050423821dc 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -790,7 +790,9 @@ static const struct phylink_mac_ops mtk_phylink_ops = {
static int mtk_mdio_init(struct mtk_eth *eth)
{
struct device_node *mii_np;
+ int clk = 25000000, max_clk = 2500000, divider = 1;
int ret;
+ u32 val;
mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
if (!mii_np) {
@@ -818,6 +820,29 @@ static int mtk_mdio_init(struct mtk_eth *eth)
eth->mii_bus->parent = eth->dev;
snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
+
+ if (!of_property_read_u32(mii_np, "clock-frequency", &val))
+ max_clk = val;
+
+ while (clk / divider > max_clk) {
+ if (divider >= 63)
+ break;
+
+ divider++;
+ };
+
+ val = mtk_r32(eth, MTK_PPSC);
+ val |= PPSC_MDC_TURBO;
+ mtk_w32(eth, val, MTK_PPSC);
+
+ /* Configure MDC Divider */
+ val = mtk_r32(eth, MTK_PPSC);
+ val &= ~PPSC_MDC_CFG;
+ val |= FIELD_PREP(PPSC_MDC_CFG, divider);
+ mtk_w32(eth, val, MTK_PPSC);
+
+ dev_dbg(eth->dev, "MDC is running on %d Hz\n", clk / divider);
+
ret = of_mdiobus_register(eth->mii_bus, mii_np);
err_put_node:
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 7230dcb29315..724815ae18a0 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -363,6 +363,11 @@
#define RX_DMA_VTAG_V2 BIT(0)
#define RX_DMA_L4_VALID_V2 BIT(2)
+/* PHY Polling and SMI Master Control registers */
+#define MTK_PPSC 0x10000
+#define PPSC_MDC_CFG GENMASK(29, 24)
+#define PPSC_MDC_TURBO BIT(20)
+
/* PHY Indirect Access Control registers */
#define MTK_PHY_IAC 0x10004
#define PHY_IAC_ACCESS BIT(31)
--
2.39.1
next prev parent reply other threads:[~2023-02-03 7:03 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-03 6:58 [PATCH 0/9] net: ethernet: mtk_eth_soc: various enhancements Daniel Golle
2023-02-03 7:00 ` [PATCH 1/9] net: ethernet: mtk_eth_soc: add support for MT7981 SoC Daniel Golle
2023-02-03 14:00 ` Andrew Lunn
2023-02-03 14:18 ` Vladimir Oltean
2023-02-03 21:51 ` Vladimir Oltean
2023-02-03 7:01 ` Daniel Golle [this message]
2023-02-03 14:06 ` [PATCH 2/9] net: ethernet: mtk_eth_soc: set MDIO bus clock frequency Andrew Lunn
2023-02-03 21:48 ` Vladimir Oltean
2023-02-03 22:15 ` Andrew Lunn
2023-02-03 22:26 ` Vladimir Oltean
2023-02-03 7:01 ` [PATCH 3/9] net: ethernet: mtk_eth_soc: reset PCS state Daniel Golle
2023-02-03 7:02 ` [PATCH 4/9] net: ethernet: mtk_eth_soc: only write values if needed Daniel Golle
2023-02-03 14:08 ` Andrew Lunn
2023-02-03 7:02 ` [PATCH 5/9] net: ethernet: mtk_eth_soc: fix RX data corruption issue Daniel Golle
2023-02-03 14:09 ` Andrew Lunn
2023-02-03 7:05 ` [PATCH 6/9] net: ethernet: mtk_eth_soc: ppe: add support for flow accounting Daniel Golle
2023-02-03 22:55 ` Vladimir Oltean
2023-02-03 7:05 ` [PATCH 7/9] net: pcs: add driver for MediaTek SGMII PCS Daniel Golle
2023-02-03 14:14 ` Andrew Lunn
2023-02-03 15:00 ` Vladimir Oltean
2023-02-03 15:21 ` Andrew Lunn
2023-02-03 7:06 ` [PATCH 8/9] net: ethernet: mtk_eth_soc: switch to external PCS driver Daniel Golle
2023-02-03 9:25 ` Bjørn Mork
2023-02-03 21:56 ` Vladimir Oltean
2023-02-03 7:06 ` [PATCH 9/9] net: dsa: mt7530: use " Daniel Golle
2023-02-03 22:19 ` Vladimir Oltean
2023-02-04 15:02 ` Daniel Golle
2023-02-04 17:13 ` Andrew Lunn
2023-02-04 23:41 ` Russell King (Oracle)
2023-02-05 12:13 ` Vladimir Oltean
2023-02-04 11:08 ` [PATCH 0/9] net: ethernet: mtk_eth_soc: various enhancements Bjørn Mork
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