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From: Florian Fainelli <f.fainelli@gmail.com>
To: "Andrew Lunn" <andrew@lunn.ch>, "Arınç ÜNAL" <arinc.unal@arinc9.com>
Cc: "DENG Qingfang" <dqfext@gmail.com>,
	"Luiz Angelo Daros de Luca" <luizluca@gmail.com>,
	"Matthias Brugger" <matthias.bgg@gmail.com>,
	"John Crispin" <john@phrozen.org>,
	"Siddhant Gupta" <siddhantgupta416@gmail.com>,
	"Ilya Lipnitskiy" <ilya.lipnitskiy@gmail.com>,
	"Sergio Paracuellos" <sergio.paracuellos@gmail.com>,
	"Felix Fietkau" <nbd@nbd.name>,
	"Sean Wang" <sean.wang@mediatek.com>,
	"Mark Lee" <Mark-MC.Lee@mediatek.com>,
	"Russell King" <linux@armlinux.org.uk>,
	"Jakub Kicinski" <kuba@kernel.org>,
	"David Miller" <davem@davemloft.net>,
	"René van Dorst" <opensource@vdorst.com>,
	"moderated list:ARM/Mediatek SoC support"
	<linux-mediatek@lists.infradead.org>,
	netdev <netdev@vger.kernel.org>,
	linux-mips@vger.kernel.org,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree@vger.kernel.org>,
	openwrt-devel@lists.openwrt.org, erkin.bozoglu@xeront.com
Subject: Re: MT7621 SoC Traffic Won't Flow on RGMII2 Bus/2nd GMAC
Date: Mon, 24 Jan 2022 09:13:38 -0800	[thread overview]
Message-ID: <acf98ec3-1120-bcc0-2a2f-85d97c48febd@gmail.com> (raw)
In-Reply-To: <Ye1zwIFUa5LPQbQm@lunn.ch>



On 1/23/2022 7:26 AM, Andrew Lunn wrote:
> On Sun, Jan 23, 2022 at 11:33:04AM +0300, Arınç ÜNAL wrote:
>> Hey Deng,
>>
>> On 23/01/2022 09:51, DENG Qingfang wrote:
>>> Hi,
>>>
>>> Do you set the ethernet pinmux correctly?
>>>
>>> &ethernet {
>>>       pinctrl-names = "default";
>>>       pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
>>> };
>>
>> This fixed it! We did have &rgmii2_pins on the gmac1 node (it was originally
>> on external_phy) so we never thought to investigate the pinctrl
>> configuration further! Turns out &rgmii2_pins needs to be defined on the
>> ethernet node instead.
> 
> PHYs are generally external, so pinmux on them makes no sense. PHYs in
> DT are not devices in the usual sense, so i don't think the driver
> core will handle pinmux for them, even if you did list them.

Not sure I understand your comment here, this is configuring the pinmux 
on the SoC side in order for the second RGMII interface's data path to work.

It is not uncommon for the same set of I/O pads to be used by different 
functions within the chip. For instance the chips I work with happily 
offer RGMII, MTSIF, PDM (I2S), TSIO on the same pads via different 
pinmuxing options.

Also, this is declaring a pinmuxing function for the Ethernet MAC, which 
is a perfectly valid use case and typically how pinmuxing is declared 
for a given SoC.
-- 
Florian

  parent reply	other threads:[~2022-01-24 17:14 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-22 18:01 Arınç ÜNAL
2022-01-23  6:51 ` DENG Qingfang
2022-01-23  8:33   ` Arınç ÜNAL
2022-01-23 15:26     ` Andrew Lunn
2022-01-23 17:48       ` Arınç ÜNAL
2022-01-24 17:13       ` Florian Fainelli [this message]
2022-01-24 17:26         ` Russell King (Oracle)
2022-01-24 17:34           ` Florian Fainelli

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