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Date:   Thu, 25 Apr 2019 12:58:32 +0200 (CEST)
From:   Thomas Gleixner <tglx@linutronix.de>
To:     David Laight <David.Laight@ACULAB.COM>
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Subject: RE: [PATCH v8 13/15] x86/split_lock: Enable split lock detection by
 default
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References: <1556134382-58814-1-git-send-email-fenghua.yu@intel.com> <1556134382-58814-14-git-send-email-fenghua.yu@intel.com> <762682ba43a0468897ff5ddbf6633d58@AcuMS.aculab.com>
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On Thu, 25 Apr 2019, David Laight wrote:

> From:  Fenghua Yu
> > Sent: 24 April 2019 20:33
> > A split locked access locks bus and degrades overall memory access
> > performance. When split lock detection feature is enumerated, enable
> > the feature by default by writing 1 to bit 29 in MSR TEST_CTL to find
> > any split lock issue.
> 
> You can't enable this by default until ALL the known potentially
> misaligned locked memory operations have been fixed.

Errm? The result will be a WARN_ON() printed and no further damage. It's
not making anything worse than it is now. In fact we just should add a

    WARN_ON_ONCE(!aligned_to_long(p)) to all the xxx_bit() operations.

so we catch them even when they do not trigger that #AC thingy.

Thanks,

	tglx