From: Paolo Abeni <pabeni@redhat.com>
To: Linus Walleij <linus.walleij@linaro.org>,
Andrew Lunn <andrew@lunn.ch>,
Vivien Didelot <vivien.didelot@gmail.com>,
Florian Fainelli <f.fainelli@gmail.com>,
Vladimir Oltean <olteanv@gmail.com>,
"David S . Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>
Cc: netdev@vger.kernel.org, "Alvin Šipraga" <alsi@bang-olufsen.dk>,
"kernel test robot" <lkp@intel.com>
Subject: Re: [PATCH v2] net: dsa: realtek: rtl8366rb: Serialize indirect PHY register access
Date: Tue, 10 May 2022 12:45:35 +0200 [thread overview]
Message-ID: <b8e254c50ca23571a640bbc230730ab4219b9308.camel@redhat.com> (raw)
In-Reply-To: <20220508230303.2522980-1-linus.walleij@linaro.org>
Hello,
On Mon, 2022-05-09 at 01:03 +0200, Linus Walleij wrote:
> From: Alvin Šipraga <alsi@bang-olufsen.dk>
>
> Lock the regmap during the whole PHY register access routines in
> rtl8366rb.
>
> Signed-off-by: Alvin Šipraga <alsi@bang-olufsen.dk>
> Reported-by: kernel test robot <lkp@intel.com>
> Tested-by: Linus Walleij <linus.walleij@linaro.org>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> ChangeLog v1->v2:
> - Make sure to always return a properly assigned error
> code on the error path in rtl8366rb_phy_read()
> found by the kernel test robot.
>
> I have tested that this does not create any regressions,
> it makes more sense to have this applied than not. First
> it is related to the same family as the other ASICs, also
> it makes perfect logical sense to enforce serialization
> of these reads/writes.
I'm unable to understand if this is targeting the 'net' or the 'net-
next' tree, could you please clarify?
If targeting 'net', adding an additional, suitable 'Fixes' tag would be
nice.
Thanks!
Paolo
prev parent reply other threads:[~2022-05-10 10:45 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-08 23:03 [PATCH v2] net: dsa: realtek: rtl8366rb: Serialize indirect PHY register access Linus Walleij
2022-05-10 10:45 ` Paolo Abeni [this message]
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