From: Benjamin Beckmeyer <beb@eks-engel.de>
To: Andrew Lunn <andrew@lunn.ch>
Cc: <netdev@vger.kernel.org>
Subject: Re: i.mx6ul with DSA in multi chip addressing mode - no MDIO access
Date: Fri, 5 Jul 2019 14:41:43 +0200 [thread overview]
Message-ID: <ba64f1f9-14c7-2835-f6e7-0dd07039fb18@eks-engel.de> (raw)
In-Reply-To: <20190704155347.GJ18473@lunn.ch>
>> &mdio0 {
>> interrupt-parent = <&gpio1>;
>> interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
>>
>> switch0: switch0@2 {
>> compatible = "marvell,mv88e6190";
>> reg = <2>;
>> pinctrl-0 = <&pinctrl_gpios>;
>> reset-gpios = <&gpio4 16 GPIO_ACTIVE_LOW>;
>> dsa,member = <0 0>;
> This is wrong. The interrupt is a switch property, not an MDIO bus
> property. So it belongs inside the switch node.
>
> Andrew
Hi Andrew,
in the documentation for Marvell DSA the interrupt properties are in
the MDIO part. Maybe the documentation for device tree is wrong or
unclear?
I switched to the kernel 5.1.16 to take advantage of your new code.
At the moment I deleted all interrupt properties from my device tree
and if I get you right now the access should be trigger all 100ms but
I have accesses within the tracing about 175 times a second.
Here is a snip from my trace without IRQ
2188000.etherne-223 [000] .... 109.932406: mdio_access: 2188000.ethernet-1 read phy:0x02 reg:0x01 val:0x40a8
2188000.etherne-223 [000] .... 109.932501: mdio_access: 2188000.ethernet-1 read phy:0x02 reg:0x00 val:0x1b64
2188000.etherne-223 [000] .... 109.933113: mdio_access: 2188000.ethernet-1 write phy:0x02 reg:0x00 val:0x9b60
2188000.etherne-223 [000] .... 109.933261: mdio_access: 2188000.ethernet-1 read phy:0x02 reg:0x00 val:0x1b60
2188000.etherne-223 [000] .... 109.933359: mdio_access: 2188000.ethernet-1 read phy:0x02 reg:0x01 val:0xc801
2188000.etherne-223 [000] .... 110.041683: mdio_access: 2188000.ethernet-1 read phy:0x02 reg:0x00 val:0x1b60
2188000.etherne-223 [000] .... 110.041817: mdio_access: 2188000.ethernet-1 write phy:0x02 reg:0x00 val:0x9b60
2188000.etherne-223 [000] .... 110.041919: mdio_access: 2188000.ethernet-1 read phy:0x02 reg:0x00 val:0x1b60
2188000.etherne-223 [000] .... 110.042025: mdio_access: 2188000.ethernet-1 read phy:0x02 reg:0x01 val:0xc801
Am I doing it right with the tracing points? I run just
echo 1 > /sys/kernel/debug/tracing/events/mdio/mdio_access/enable
cat /sys/kernel/debug/tracing/trace
Here is the another device tree I tried, but with this I get accesses
on the bus in about every 50 microseconds!
--snip
&mdio0 {
switch0: switch0@2 {
compatible = "marvell,mv88e6190";
reg = <2>;
pinctrl-0 = <&pinctrl_switch_irq>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
dsa,member = <0 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
--snip
Here is a snip from my trace with IRQ.
irq/54-2188000.-223 [000] .... 958.940744: mdio_access: 2188000.ethernet-1 read phy:0x02 reg:0x00 val:0x1b64
irq/54-2188000.-223 [000] .... 958.940800: mdio_access: 2188000.ethernet-1 write phy:0x02 reg:0x00 val:0x9b60
irq/54-2188000.-223 [000] .... 958.940857: mdio_access: 2188000.ethernet-1 read phy:0x02 reg:0x00 val:0x1b60
irq/54-2188000.-223 [000] .... 958.940914: mdio_access: 2188000.ethernet-1 read phy:0x02 reg:0x01 val:0xc801
irq/54-2188000.-223 [000] .... 958.940984: mdio_access: 2188000.ethernet-1 read phy:0x02 reg:0x00 val:0x1b60
irq/54-2188000.-223 [000] .... 958.941043: mdio_access: 2188000.ethernet-1 write phy:0x02 reg:0x00 val:0x9b60
irq/54-2188000.-223 [000] .... 958.941100: mdio_access: 2188000.ethernet-1 read phy:0x02 reg:0x00 val:0x1b60
irq/54-2188000.-223 [000] .... 958.941158: mdio_access: 2188000.ethernet-1 read phy:0x02 reg:0x01 val:0xc801
irq/54-2188000.-223 [000] .... 958.941218: mdio_access: 2188000.ethernet-1 read phy:0x02 reg:0x00 val:0x1b60
irq/54-2188000.-223 [000] .... 958.941276: mdio_access: 2188000.ethernet-1 write phy:0x02 reg:0x00 val:0x9b64
Thanks,
Benny
next prev parent reply other threads:[~2019-07-05 12:41 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-03 13:10 i.mx6ul with DSA in multi chip addressing mode - no MDIO access Benjamin Beckmeyer
2019-07-03 15:55 ` Andrew Lunn
2019-07-04 4:33 ` Benjamin Beckmeyer
2019-07-04 8:54 ` Benjamin Beckmeyer
2019-07-04 13:27 ` Andrew Lunn
2019-07-04 14:39 ` Benjamin Beckmeyer
2019-07-04 15:53 ` Andrew Lunn
2019-07-05 12:41 ` Benjamin Beckmeyer [this message]
2019-07-05 14:36 ` Andrew Lunn
2019-07-08 13:55 ` Benjamin Beckmeyer
2019-07-08 14:57 ` Andrew Lunn
2019-07-09 13:20 ` Benjamin Beckmeyer
2019-07-09 13:52 ` Andrew Lunn
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