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([2600:1700:dfe0:49f0:802c:b332:26e0:e0aa]) by smtp.gmail.com with ESMTPSA id 139sm3592985qkj.44.2021.10.10.18.49.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 10 Oct 2021 18:49:49 -0700 (PDT) Message-ID: Date: Sun, 10 Oct 2021 18:49:46 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.1.2 Subject: Re: [net-next PATCH v5 03/14] net: dsa: qca8k: add support for sgmii falling edge Content-Language: en-US To: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Matthew Hagan References: <20211011013024.569-1-ansuelsmth@gmail.com> <20211011013024.569-4-ansuelsmth@gmail.com> From: Florian Fainelli In-Reply-To: <20211011013024.569-4-ansuelsmth@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On 10/10/2021 6:30 PM, Ansuel Smith wrote: > Add support for this in the qca8k driver. Also add support for SGMII > rx/tx clock falling edge. This is only present for pad0, pad5 and > pad6 have these bit reserved from Documentation. Add a comment that this > is hardcoded to PAD0 as qca8327/28/34/37 have an unique sgmii line and > setting falling in port0 applies to both configuration with sgmii used > for port0 or port6. > > Signed-off-by: Matthew Hagan > Signed-off-by: Ansuel Smith > --- > drivers/net/dsa/qca8k.c | 57 +++++++++++++++++++++++++++++++++++++++++ > drivers/net/dsa/qca8k.h | 4 +++ > 2 files changed, 61 insertions(+) > > diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c > index a892b897cd0d..e335a4cfcb75 100644 > --- a/drivers/net/dsa/qca8k.c > +++ b/drivers/net/dsa/qca8k.c > @@ -977,6 +977,36 @@ qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv) > return ret; > } > > +static int > +qca8k_parse_port_config(struct qca8k_priv *priv) > +{ > + struct device_node *port_dn; > + phy_interface_t mode; > + struct dsa_port *dp; > + int port; > + > + /* We have 2 CPU port. Check them */ > + for (port = 0; port < QCA8K_NUM_PORTS; port++) { > + /* Skip every other port */ > + if (port != 0 && port != 6) > + continue; > + > + dp = dsa_to_port(priv->ds, port); > + port_dn = dp->dn; You should probably have an: if (!of_device_is_available(port_dn)) continue to skip over ports being disabled, which could presumably happen in a sparsely populated switch for instance. > + > + of_get_phy_mode(port_dn, &mode); This function returns an error that you are not checking. > + if (mode == PHY_INTERFACE_MODE_SGMII) { > + if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge")) > + priv->sgmii_tx_clk_falling_edge = true; > + > + if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge")) > + priv->sgmii_rx_clk_falling_edge = true; > + } > + } > + > + return 0; > +} > + > static int > qca8k_setup(struct dsa_switch *ds) > { > @@ -990,6 +1020,11 @@ qca8k_setup(struct dsa_switch *ds) > return -EINVAL; > } > > + /* Parse CPU port config to be later used in phy_link mac_config */ > + ret = qca8k_parse_port_config(priv); > + if (ret) > + return ret; > + > mutex_init(&priv->reg_mutex); > > /* Start by setting up the register mapping */ > @@ -1274,6 +1309,28 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, > } > > qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val); > + > + /* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and > + * falling edge is set writing in the PORT0 PAD reg > + */ > + if (priv->switch_id == QCA8K_ID_QCA8327 || > + priv->switch_id == QCA8K_ID_QCA8337) > + reg = QCA8K_REG_PORT0_PAD_CTRL; > + > + val = 0; > + > + /* SGMII Clock phase configuration */ > + if (priv->sgmii_rx_clk_falling_edge) > + val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE; > + > + if (priv->sgmii_tx_clk_falling_edge) > + val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE; > + > + if (val) > + ret = qca8k_rmw(priv, reg, > + QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE | > + QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE, > + val); > break; > default: > dev_err(ds->dev, "xMII mode %s not supported for port %d\n", > diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h > index fc7db94cc0c9..bc9c89dd7e71 100644 > --- a/drivers/net/dsa/qca8k.h > +++ b/drivers/net/dsa/qca8k.h > @@ -35,6 +35,8 @@ > #define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8) > #define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8) > #define QCA8K_REG_PORT0_PAD_CTRL 0x004 > +#define QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE BIT(19) > +#define QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE BIT(18) > #define QCA8K_REG_PORT5_PAD_CTRL 0x008 > #define QCA8K_REG_PORT6_PAD_CTRL 0x00c > #define QCA8K_PORT_PAD_RGMII_EN BIT(26) > @@ -260,6 +262,8 @@ struct qca8k_priv { > u8 switch_revision; > u8 rgmii_tx_delay; > u8 rgmii_rx_delay; > + bool sgmii_rx_clk_falling_edge; > + bool sgmii_tx_clk_falling_edge; > bool legacy_phy_port_mapping; > struct regmap *regmap; > struct mii_bus *bus; > -- Florian