[Nouveau] [PATCH 1/6] drm/gem: Remove BUG_ON in drm_gem_private_object_init

[Nouveau] [PATCH 1/6] drm/gem: Remove BUG_ON in drm_gem_private_object_init

[Somalapuram Amaranath]

ttm_resource can allocate size in bytes to support less than page size.

Signed-off-by: Somalapuram Amaranath <Amaranath.Somalapuram@amd.com>
---
 drivers/gpu/drm/drm_gem.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 59a0bb5ebd85..ee8b5c2b6c60 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -152,8 +152,6 @@ EXPORT_SYMBOL(drm_gem_object_init);
 void drm_gem_private_object_init(struct drm_device *dev,
 				 struct drm_gem_object *obj, size_t size)
 {
-	BUG_ON((size & (PAGE_SIZE - 1)) != 0);
-
 	obj->dev = dev;
 	obj->filp = NULL;
 
-- 
2.32.0

[Nouveau] [PATCH 2/6] drm/amdgpu: Remove TTM resource->start visible VRAM condition

[Somalapuram Amaranath]

Use amdgpu_bo_in_cpu_visible_vram() instead.

Signed-off-by: Somalapuram Amaranath <Amaranath.Somalapuram@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 981010de0a28..d835ee2131d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -600,7 +600,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
 
 	if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 	    bo->tbo.resource->mem_type == TTM_PL_VRAM &&
-	    bo->tbo.resource->start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
+	    amdgpu_bo_in_cpu_visible_vram(bo))
 		amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
 					     ctx.bytes_moved);
 	else
@@ -1346,7 +1346,6 @@ vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 	struct ttm_operation_ctx ctx = { false, false };
 	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
-	unsigned long offset;
 	int r;
 
 	/* Remember that this BO was accessed by the CPU */
@@ -1355,8 +1354,7 @@ vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 	if (bo->resource->mem_type != TTM_PL_VRAM)
 		return 0;
 
-	offset = bo->resource->start << PAGE_SHIFT;
-	if ((offset + bo->base.size) <= adev->gmc.visible_vram_size)
+	if (amdgpu_bo_in_cpu_visible_vram(abo))
 		return 0;
 
 	/* Can't move a pinned BO to visible VRAM */
@@ -1378,10 +1376,9 @@ vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 	else if (unlikely(r))
 		return VM_FAULT_SIGBUS;
 
-	offset = bo->resource->start << PAGE_SHIFT;
 	/* this should never happen */
 	if (bo->resource->mem_type == TTM_PL_VRAM &&
-	    (offset + bo->base.size) > adev->gmc.visible_vram_size)
+	    amdgpu_bo_in_cpu_visible_vram(abo))
 		return VM_FAULT_SIGBUS;
 
 	ttm_bo_move_to_lru_tail_unlocked(bo);
-- 
2.32.0

[Nouveau] [PATCH 3/6] drm/ttm: Change the meaning of resource->start from pfn to bytes

[Somalapuram Amaranath]

Change resource->start from pfn to bytes to
allow allocating objects smaller than a page.
Change all DRM drivers using ttm_resource start and size pfn to bytes.
Change amdgpu_res_first() cur->start, cur->size from pfn to bytes.
Replacing ttm_resource resource->start field with cursor.start.
Change amdgpu_gtt_mgr_new() allocation from pfn to bytes.

Signed-off-by: Somalapuram Amaranath <Amaranath.Somalapuram@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c         | 13 +++++++------
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c          |  4 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h      |  8 ++++----
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c             | 10 +++++++---
 .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c   |  6 +++++-
 drivers/gpu/drm/drm_gem_vram_helper.c               |  2 +-
 drivers/gpu/drm/nouveau/nouveau_bo.c                | 13 ++++++-------
 drivers/gpu/drm/nouveau/nouveau_bo0039.c            |  4 ++--
 drivers/gpu/drm/nouveau/nouveau_mem.c               | 10 +++++-----
 drivers/gpu/drm/nouveau/nouveau_ttm.c               |  2 +-
 drivers/gpu/drm/nouveau/nv17_fence.c                |  2 +-
 drivers/gpu/drm/nouveau/nv50_fence.c                |  2 +-
 drivers/gpu/drm/qxl/qxl_drv.h                       |  2 +-
 drivers/gpu/drm/qxl/qxl_object.c                    |  2 +-
 drivers/gpu/drm/qxl/qxl_ttm.c                       |  5 ++---
 drivers/gpu/drm/radeon/radeon_object.c              |  6 +++---
 drivers/gpu/drm/radeon/radeon_object.h              |  2 +-
 drivers/gpu/drm/radeon/radeon_ttm.c                 | 13 ++++++-------
 drivers/gpu/drm/radeon/radeon_vm.c                  |  2 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_bo.c                  |  4 ++--
 drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c                 |  2 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c             |  2 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c          |  3 +--
 23 files changed, 63 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 44367f03316f..a1fbfc5984d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -116,7 +116,6 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager *man,
 			      struct ttm_resource **res)
 {
 	struct amdgpu_gtt_mgr *mgr = to_gtt_mgr(man);
-	uint32_t num_pages = PFN_UP(tbo->base.size);
 	struct ttm_range_mgr_node *node;
 	int r;
 
@@ -134,8 +133,10 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager *man,
 	if (place->lpfn) {
 		spin_lock(&mgr->lock);
 		r = drm_mm_insert_node_in_range(&mgr->mm, &node->mm_nodes[0],
-						num_pages, tbo->page_alignment,
-						0, place->fpfn, place->lpfn,
+						tbo->base.size,
+						tbo->page_alignment << PAGE_SHIFT, 0,
+						place->fpfn << PAGE_SHIFT,
+						place->lpfn << PAGE_SHIFT,
 						DRM_MM_INSERT_BEST);
 		spin_unlock(&mgr->lock);
 		if (unlikely(r))
@@ -144,7 +145,7 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager *man,
 		node->base.start = node->mm_nodes[0].start;
 	} else {
 		node->mm_nodes[0].start = 0;
-		node->mm_nodes[0].size = PFN_UP(node->base.size);
+		node->mm_nodes[0].size = node->base.size;
 		node->base.start = AMDGPU_BO_INVALID_OFFSET;
 	}
 
@@ -285,8 +286,8 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size)
 
 	ttm_resource_manager_init(man, &adev->mman.bdev, gtt_size);
 
-	start = AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS;
-	size = (adev->gmc.gart_size >> PAGE_SHIFT) - start;
+	start = (AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS) << PAGE_SHIFT;
+	size = adev->gmc.gart_size - start;
 	drm_mm_init(&mgr->mm, start, size);
 	spin_lock_init(&mgr->lock);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index d835ee2131d2..f5d5eee09cea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1488,9 +1488,11 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
 {
 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+	struct amdgpu_res_cursor cursor;
 	uint64_t offset;
 
-	offset = (bo->tbo.resource->start << PAGE_SHIFT) +
+	amdgpu_res_first(bo->tbo.resource, 0, bo->tbo.resource->size, &cursor);
+	offset = cursor.start +
 		 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type);
 
 	return amdgpu_gmc_sign_extend(offset);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
index 5c4f93ee0c57..5c78f0b09351 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
@@ -94,8 +94,8 @@ static inline void amdgpu_res_first(struct ttm_resource *res,
 		while (start >= node->size << PAGE_SHIFT)
 			start -= node++->size << PAGE_SHIFT;
 
-		cur->start = (node->start << PAGE_SHIFT) + start;
-		cur->size = min((node->size << PAGE_SHIFT) - start, size);
+		cur->start = node->start + start;
+		cur->size = min(node->size - start, size);
 		cur->remaining = size;
 		cur->node = node;
 		break;
@@ -155,8 +155,8 @@ static inline void amdgpu_res_next(struct amdgpu_res_cursor *cur, uint64_t size)
 		node = cur->node;
 
 		cur->node = ++node;
-		cur->start = node->start << PAGE_SHIFT;
-		cur->size = min(node->size << PAGE_SHIFT, cur->remaining);
+		cur->start = node->start;
+		cur->size = min(node->size, cur->remaining);
 		break;
 	default:
 		return;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 2cd081cbf706..6b270d4662a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -845,6 +845,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
 {
 	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
+	struct amdgpu_res_cursor cursor;
 	uint64_t flags;
 	int r;
 
@@ -892,7 +893,8 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
 	flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
 
 	/* bind pages into GART page tables */
-	gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
+	amdgpu_res_first(bo_mem, 0, bo_mem->size, &cursor);
+	gtt->offset = cursor.start;
 	amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 			 gtt->ttm.dma_address, flags);
 	gtt->bound = true;
@@ -912,6 +914,7 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 	struct ttm_operation_ctx ctx = { false, false };
 	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
+	struct amdgpu_res_cursor cursor;
 	struct ttm_placement placement;
 	struct ttm_place placements;
 	struct ttm_resource *tmp;
@@ -923,7 +926,7 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 
 	addr = amdgpu_gmc_agp_addr(bo);
 	if (addr != AMDGPU_BO_INVALID_OFFSET) {
-		bo->resource->start = addr >> PAGE_SHIFT;
+		bo->resource->start = addr;
 		return 0;
 	}
 
@@ -945,7 +948,8 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp);
 
 	/* Bind pages */
-	gtt->offset = (u64)tmp->start << PAGE_SHIFT;
+	amdgpu_res_first(tmp, 0, tmp->size, &cursor);
+	gtt->offset = cursor.start;
 	amdgpu_ttm_gart_bind(adev, bo, flags);
 	amdgpu_gart_invalidate_tlb(adev);
 	ttm_resource_free(bo, &bo->resource);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index c06ada0844ba..9114393d2ee6 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -200,8 +200,12 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q,
 	queue_input.wptr_addr = (uint64_t)q->properties.write_ptr;
 
 	if (q->wptr_bo) {
+		struct amdgpu_res_cursor cursor;
+
 		wptr_addr_off = (uint64_t)q->properties.write_ptr & (PAGE_SIZE - 1);
-		queue_input.wptr_mc_addr = ((uint64_t)q->wptr_bo->tbo.resource->start << PAGE_SHIFT) + wptr_addr_off;
+		amdgpu_res_first(q->wptr_bo->tbo.resource, 0,
+				 q->wptr_bo->tbo.resource->size, &cursor);
+		queue_input.wptr_mc_addr = cursor.start + wptr_addr_off;
 	}
 
 	queue_input.is_kfd_process = 1;
diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c b/drivers/gpu/drm/drm_gem_vram_helper.c
index d40b3edb52d0..e7be562790de 100644
--- a/drivers/gpu/drm/drm_gem_vram_helper.c
+++ b/drivers/gpu/drm/drm_gem_vram_helper.c
@@ -275,7 +275,7 @@ s64 drm_gem_vram_offset(struct drm_gem_vram_object *gbo)
 {
 	if (WARN_ON_ONCE(!gbo->bo.pin_count))
 		return (s64)-ENODEV;
-	return drm_gem_vram_pg_offset(gbo) << PAGE_SHIFT;
+	return drm_gem_vram_pg_offset(gbo);
 }
 EXPORT_SYMBOL(drm_gem_vram_offset);
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index c2ec91cc845d..89fada6c2e11 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -946,7 +946,7 @@ static void nouveau_bo_move_ntfy(struct ttm_buffer_object *bo,
 	}
 
 	if (new_reg)
-		nvbo->offset = (new_reg->start << PAGE_SHIFT);
+		nvbo->offset = new_reg->start;
 
 }
 
@@ -957,7 +957,7 @@ nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg,
 	struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 	struct drm_device *dev = drm->dev;
 	struct nouveau_bo *nvbo = nouveau_bo(bo);
-	u64 offset = new_reg->start << PAGE_SHIFT;
+	u64 offset = new_reg->start;
 
 	*new_tile = NULL;
 	if (new_reg->mem_type != TTM_PL_VRAM)
@@ -1118,8 +1118,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *reg)
 	case TTM_PL_TT:
 #if IS_ENABLED(CONFIG_AGP)
 		if (drm->agp.bridge) {
-			reg->bus.offset = (reg->start << PAGE_SHIFT) +
-				drm->agp.base;
+			reg->bus.offset = reg->start + drm->agp.base;
 			reg->bus.is_iomem = !drm->agp.cma;
 			reg->bus.caching = ttm_write_combined;
 		}
@@ -1132,7 +1131,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *reg)
 		}
 		fallthrough;	/* tiled memory */
 	case TTM_PL_VRAM:
-		reg->bus.offset = (reg->start << PAGE_SHIFT) +
+		reg->bus.offset = reg->start +
 			device->func->resource_addr(device, 1);
 		reg->bus.is_iomem = true;
 
@@ -1222,7 +1221,7 @@ vm_fault_t nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
 	struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 	struct nouveau_bo *nvbo = nouveau_bo(bo);
 	struct nvkm_device *device = nvxx_device(&drm->client.device);
-	u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
+	u32 mappable = device->func->resource_size(device, 1);
 	int i, ret;
 
 	/* as long as the bo isn't in vram, and isn't tiled, we've got
@@ -1241,7 +1240,7 @@ vm_fault_t nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
 	} else {
 		/* make sure bo is in mappable vram */
 		if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
-		    bo->resource->start + PFN_UP(bo->resource->size) < mappable)
+		    bo->resource->start + bo->resource->size < mappable)
 			return 0;
 
 		for (i = 0; i < nvbo->placement.num_placement; ++i) {
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo0039.c b/drivers/gpu/drm/nouveau/nouveau_bo0039.c
index e2ce44adaa5c..41197312f82f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo0039.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo0039.c
@@ -49,9 +49,9 @@ nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 {
 	struct nvif_push *push = chan->chan.push;
 	u32 src_ctxdma = nouveau_bo_mem_ctxdma(bo, chan, old_reg);
-	u32 src_offset = old_reg->start << PAGE_SHIFT;
+	u32 src_offset = old_reg->start;
 	u32 dst_ctxdma = nouveau_bo_mem_ctxdma(bo, chan, new_reg);
-	u32 dst_offset = new_reg->start << PAGE_SHIFT;
+	u32 dst_offset = new_reg->start;
 	u32 page_count = PFN_UP(new_reg->size);
 	int ret;
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 25f31d5169e5..d31cc3b069d8 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -158,7 +158,7 @@ nouveau_mem_vram(struct ttm_resource *reg, bool contig, u8 page)
 	}
 	mutex_unlock(&drm->master.lock);
 
-	reg->start = mem->mem.addr >> PAGE_SHIFT;
+	reg->start = mem->mem.addr;
 	return ret;
 }
 
@@ -197,8 +197,8 @@ nouveau_mem_intersects(struct ttm_resource *res,
 	u32 num_pages = PFN_UP(size);
 
 	/* Don't evict BOs outside of the requested placement range */
-	if (place->fpfn >= (res->start + num_pages) ||
-	    (place->lpfn && place->lpfn <= res->start))
+	if (place->fpfn >= ((res->start >> PAGE_SHIFT) + num_pages) ||
+	    (place->lpfn && place->lpfn <= (res->start >> PAGE_SHIFT)))
 		return false;
 
 	return true;
@@ -211,8 +211,8 @@ nouveau_mem_compatible(struct ttm_resource *res,
 {
 	u32 num_pages = PFN_UP(size);
 
-	if (res->start < place->fpfn ||
-	    (place->lpfn && (res->start + num_pages) > place->lpfn))
+	if ((res->start >> PAGE_SHIFT) < place->fpfn ||
+	    (place->lpfn && ((res->start >> PAGE_SHIFT) + num_pages) > place->lpfn))
 		return false;
 
 	return true;
diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c
index 1469a88910e4..2127b98e033a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_ttm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c
@@ -145,7 +145,7 @@ nv04_gart_manager_new(struct ttm_resource_manager *man,
 		return ret;
 	}
 
-	(*res)->start = mem->vma[0].addr >> PAGE_SHIFT;
+	(*res)->start = mem->vma[0].addr;
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/nv17_fence.c b/drivers/gpu/drm/nouveau/nv17_fence.c
index 07c2e0878c24..b6567e5f769c 100644
--- a/drivers/gpu/drm/nouveau/nv17_fence.c
+++ b/drivers/gpu/drm/nouveau/nv17_fence.c
@@ -79,7 +79,7 @@ nv17_fence_context_new(struct nouveau_channel *chan)
 	struct nv10_fence_priv *priv = chan->drm->fence;
 	struct ttm_resource *reg = priv->bo->bo.resource;
 	struct nv10_fence_chan *fctx;
-	u32 start = reg->start * PAGE_SIZE;
+	u32 start = reg->start;
 	u32 limit = start + priv->bo->bo.base.size - 1;
 	int ret = 0;
 
diff --git a/drivers/gpu/drm/nouveau/nv50_fence.c b/drivers/gpu/drm/nouveau/nv50_fence.c
index ea1e1f480bfe..c3f1df834bb9 100644
--- a/drivers/gpu/drm/nouveau/nv50_fence.c
+++ b/drivers/gpu/drm/nouveau/nv50_fence.c
@@ -38,7 +38,7 @@ nv50_fence_context_new(struct nouveau_channel *chan)
 	struct nv10_fence_priv *priv = chan->drm->fence;
 	struct nv10_fence_chan *fctx;
 	struct ttm_resource *reg = priv->bo->bo.resource;
-	u32 start = reg->start * PAGE_SIZE;
+	u32 start = reg->start;
 	u32 limit = start + priv->bo->bo.base.size - 1;
 	int ret;
 
diff --git a/drivers/gpu/drm/qxl/qxl_drv.h b/drivers/gpu/drm/qxl/qxl_drv.h
index ea993d7162e8..994996e6a623 100644
--- a/drivers/gpu/drm/qxl/qxl_drv.h
+++ b/drivers/gpu/drm/qxl/qxl_drv.h
@@ -289,7 +289,7 @@ qxl_bo_physical_address(struct qxl_device *qdev, struct qxl_bo *bo,
 
        /* TODO - need to hold one of the locks to read bo->tbo.resource->start */
 
-	return slot->high_bits | ((bo->tbo.resource->start << PAGE_SHIFT) + offset);
+	return slot->high_bits | (bo->tbo.resource->start + offset);
 }
 
 /* qxl_display.c */
diff --git a/drivers/gpu/drm/qxl/qxl_object.c b/drivers/gpu/drm/qxl/qxl_object.c
index 06a58dad5f5c..657b9995f4f6 100644
--- a/drivers/gpu/drm/qxl/qxl_object.c
+++ b/drivers/gpu/drm/qxl/qxl_object.c
@@ -220,7 +220,7 @@ void *qxl_bo_kmap_atomic_page(struct qxl_device *qdev,
 	else
 		goto fallback;
 
-	offset = bo->tbo.resource->start << PAGE_SHIFT;
+	offset = bo->tbo.resource->start;
 	return io_mapping_map_atomic_wc(map, offset + page_offset);
 fallback:
 	if (bo->kptr) {
diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c
index a92a5b0d4c25..31f96c7d89b4 100644
--- a/drivers/gpu/drm/qxl/qxl_ttm.c
+++ b/drivers/gpu/drm/qxl/qxl_ttm.c
@@ -81,13 +81,12 @@ int qxl_ttm_io_mem_reserve(struct ttm_device *bdev,
 		return 0;
 	case TTM_PL_VRAM:
 		mem->bus.is_iomem = true;
-		mem->bus.offset = (mem->start << PAGE_SHIFT) + qdev->vram_base;
+		mem->bus.offset = mem->start + qdev->vram_base;
 		mem->bus.caching = ttm_write_combined;
 		break;
 	case TTM_PL_PRIV:
 		mem->bus.is_iomem = true;
-		mem->bus.offset = (mem->start << PAGE_SHIFT) +
-			qdev->surfaceram_base;
+		mem->bus.offset = mem->start + qdev->surfaceram_base;
 		mem->bus.caching = ttm_write_combined;
 		break;
 	default:
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 10c0fbd9d2b4..83d50c72aeeb 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -588,7 +588,7 @@ int radeon_bo_get_surface_reg(struct radeon_bo *bo)
 
 out:
 	radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
-			       bo->tbo.resource->start << PAGE_SHIFT,
+			       bo->tbo.resource->start,
 			       bo->tbo.base.size);
 	return 0;
 }
@@ -738,7 +738,7 @@ vm_fault_t radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 		return 0;
 
 	size = bo->resource->size;
-	offset = bo->resource->start << PAGE_SHIFT;
+	offset = bo->resource->start;
 	if ((offset + size) <= rdev->mc.visible_vram_size)
 		return 0;
 
@@ -760,7 +760,7 @@ vm_fault_t radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 		radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
 		r = ttm_bo_validate(bo, &rbo->placement, &ctx);
 	} else if (likely(!r)) {
-		offset = bo->resource->start << PAGE_SHIFT;
+		offset = bo->resource->start;
 		/* this should never happen */
 		if ((offset + size) > rdev->mc.visible_vram_size)
 			return VM_FAULT_SIGBUS;
diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h
index 0a6ef49e990a..6e0002e08c57 100644
--- a/drivers/gpu/drm/radeon/radeon_object.h
+++ b/drivers/gpu/drm/radeon/radeon_object.h
@@ -104,7 +104,7 @@ static inline u64 radeon_bo_gpu_offset(struct radeon_bo *bo)
 		break;
 	}
 
-	return (bo->tbo.resource->start << PAGE_SHIFT) + start;
+	return bo->tbo.resource->start + start;
 }
 
 static inline unsigned long radeon_bo_size(struct radeon_bo *bo)
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 67075c85f847..777d38b211d2 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -104,7 +104,7 @@ static void radeon_evict_flags(struct ttm_buffer_object *bo,
 		if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
 			radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
 		else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size &&
-			 bo->resource->start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) {
+			 bo->resource->start < rbo->rdev->mc.visible_vram_size) {
 			unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 			int i;
 
@@ -149,8 +149,8 @@ static int radeon_move_blit(struct ttm_buffer_object *bo,
 
 	rdev = radeon_get_rdev(bo->bdev);
 	ridx = radeon_copy_ring_index(rdev);
-	old_start = (u64)old_mem->start << PAGE_SHIFT;
-	new_start = (u64)new_mem->start << PAGE_SHIFT;
+	old_start = (u64)old_mem->start;
+	new_start = (u64)new_mem->start;
 
 	switch (old_mem->mem_type) {
 	case TTM_PL_VRAM:
@@ -274,15 +274,14 @@ static int radeon_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resourc
 #if IS_ENABLED(CONFIG_AGP)
 		if (rdev->flags & RADEON_IS_AGP) {
 			/* RADEON_IS_AGP is set only if AGP is active */
-			mem->bus.offset = (mem->start << PAGE_SHIFT) +
-				rdev->mc.agp_base;
+			mem->bus.offset = mem->start + rdev->mc.agp_base;
 			mem->bus.is_iomem = !rdev->agp->cant_use_aperture;
 			mem->bus.caching = ttm_write_combined;
 		}
 #endif
 		break;
 	case TTM_PL_VRAM:
-		mem->bus.offset = mem->start << PAGE_SHIFT;
+		mem->bus.offset = mem->start;
 		/* check if it's visible */
 		if ((mem->bus.offset + bus_size) > rdev->mc.visible_vram_size)
 			return -EINVAL;
@@ -443,7 +442,7 @@ static int radeon_ttm_backend_bind(struct ttm_device *bdev,
 		flags &= ~RADEON_GART_PAGE_WRITE;
 	}
 
-	gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
+	gtt->offset = (unsigned long)bo_mem->start;
 	if (!ttm->num_pages) {
 		WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
 		     ttm->num_pages, bo_mem, ttm);
diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c
index 987cabbf1318..27ba2f6c4ac5 100644
--- a/drivers/gpu/drm/radeon/radeon_vm.c
+++ b/drivers/gpu/drm/radeon/radeon_vm.c
@@ -945,7 +945,7 @@ int radeon_vm_bo_update(struct radeon_device *rdev,
 		bo_va->flags &= ~RADEON_VM_PAGE_WRITEABLE;
 
 	if (mem) {
-		addr = (u64)mem->start << PAGE_SHIFT;
+		addr = (u64)mem->start;
 		if (mem->mem_type != TTM_PL_SYSTEM)
 			bo_va->flags |= RADEON_VM_PAGE_VALID;
 
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c b/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
index 9bf1f9d2f9b6..f58af9753ca1 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
@@ -200,7 +200,7 @@ int vmw_bo_pin_in_start_of_vram(struct vmw_private *dev_priv,
 	 * that situation.
 	 */
 	if (bo->resource->mem_type == TTM_PL_VRAM &&
-	    bo->resource->start < PFN_UP(bo->resource->size) &&
+	    bo->resource->start < bo->resource->size &&
 	    bo->resource->start > 0 &&
 	    buf->base.pin_count == 0) {
 		ctx.interruptible = false;
@@ -263,7 +263,7 @@ void vmw_bo_get_guest_ptr(const struct ttm_buffer_object *bo,
 {
 	if (bo->resource->mem_type == TTM_PL_VRAM) {
 		ptr->gmrId = SVGA_GMR_FRAMEBUFFER;
-		ptr->offset = bo->resource->start << PAGE_SHIFT;
+		ptr->offset = bo->resource->start;
 	} else {
 		ptr->gmrId = bo->resource->start;
 		ptr->offset = 0;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c b/drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c
index 162dfeb1cc5a..4883f8fc71f2 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c
@@ -584,7 +584,7 @@ static int vmw_cmd_emit_dummy_legacy_query(struct vmw_private *dev_priv,
 
 	if (bo->resource->mem_type == TTM_PL_VRAM) {
 		cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER;
-		cmd->body.guestResult.offset = bo->resource->start << PAGE_SHIFT;
+		cmd->body.guestResult.offset = bo->resource->start;
 	} else {
 		cmd->body.guestResult.gmrId = bo->resource->start;
 		cmd->body.guestResult.offset = 0;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
index 9359e8dfbac2..c882990ac361 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
@@ -3755,7 +3755,7 @@ static void vmw_apply_relocations(struct vmw_sw_context *sw_context)
 		bo = &reloc->vbo->base;
 		switch (bo->resource->mem_type) {
 		case TTM_PL_VRAM:
-			reloc->location->offset += bo->resource->start << PAGE_SHIFT;
+			reloc->location->offset += bo->resource->start;
 			reloc->location->gmrId = SVGA_GMR_FRAMEBUFFER;
 			break;
 		case VMW_PL_GMR:
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
index 856a352a72a6..3b3cb872858b 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
@@ -543,8 +543,7 @@ static int vmw_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *
 	case VMW_PL_MOB:
 		return 0;
 	case TTM_PL_VRAM:
-		mem->bus.offset = (mem->start << PAGE_SHIFT) +
-			dev_priv->vram_start;
+		mem->bus.offset = mem->start + dev_priv->vram_start;
 		mem->bus.is_iomem = true;
 		mem->bus.caching = ttm_cached;
 		break;
-- 
2.32.0

[Nouveau] [PATCH 4/6] drm/ttm: Change the parameters of ttm_range_man_init() from pages to bytes

[Somalapuram Amaranath]

Change the parameters of ttm_range_man_init_nocheck()
size from page size to byte size.
Cleanup the PAGE_SHIFT operation on the depended caller functions.

Signed-off-by: Somalapuram Amaranath <Amaranath.Somalapuram@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 ++--
 drivers/gpu/drm/drm_gem_vram_helper.c   | 2 +-
 drivers/gpu/drm/radeon/radeon_ttm.c     | 4 ++--
 drivers/gpu/drm/ttm/ttm_range_manager.c | 8 ++++----
 drivers/gpu/drm/vmwgfx/vmwgfx_drv.c     | 2 +-
 include/drm/ttm/ttm_range_manager.h     | 6 +++---
 6 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 6b270d4662a3..f0dabdfd3780 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -75,10 +75,10 @@ static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
 
 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
 				    unsigned int type,
-				    uint64_t size_in_page)
+				    uint64_t size)
 {
 	return ttm_range_man_init(&adev->mman.bdev, type,
-				  false, size_in_page);
+				  false, size << PAGE_SHIFT);
 }
 
 /**
diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c b/drivers/gpu/drm/drm_gem_vram_helper.c
index e7be562790de..db1915414e4a 100644
--- a/drivers/gpu/drm/drm_gem_vram_helper.c
+++ b/drivers/gpu/drm/drm_gem_vram_helper.c
@@ -999,7 +999,7 @@ static int drm_vram_mm_init(struct drm_vram_mm *vmm, struct drm_device *dev,
 		return ret;
 
 	ret = ttm_range_man_init(&vmm->bdev, TTM_PL_VRAM,
-				 false, vram_size >> PAGE_SHIFT);
+				 false, vram_size);
 	if (ret)
 		return ret;
 
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 777d38b211d2..aa8785b6b1e8 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -70,13 +70,13 @@ struct radeon_device *radeon_get_rdev(struct ttm_device *bdev)
 static int radeon_ttm_init_vram(struct radeon_device *rdev)
 {
 	return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_VRAM,
-				  false, rdev->mc.real_vram_size >> PAGE_SHIFT);
+				  false, rdev->mc.real_vram_size);
 }
 
 static int radeon_ttm_init_gtt(struct radeon_device *rdev)
 {
 	return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_TT,
-				  true, rdev->mc.gtt_size >> PAGE_SHIFT);
+				  true, rdev->mc.gtt_size);
 }
 
 static void radeon_evict_flags(struct ttm_buffer_object *bo,
diff --git a/drivers/gpu/drm/ttm/ttm_range_manager.c b/drivers/gpu/drm/ttm/ttm_range_manager.c
index ae11d07eb63a..62fddcc59f02 100644
--- a/drivers/gpu/drm/ttm/ttm_range_manager.c
+++ b/drivers/gpu/drm/ttm/ttm_range_manager.c
@@ -169,7 +169,7 @@ static const struct ttm_resource_manager_func ttm_range_manager_func = {
  * @bdev: ttm device
  * @type: memory manager type
  * @use_tt: if the memory manager uses tt
- * @p_size: size of area to be managed in pages.
+ * @size: size of area to be managed in bytes.
  *
  * The range manager is installed for this device in the type slot.
  *
@@ -177,7 +177,7 @@ static const struct ttm_resource_manager_func ttm_range_manager_func = {
  */
 int ttm_range_man_init_nocheck(struct ttm_device *bdev,
 		       unsigned type, bool use_tt,
-		       unsigned long p_size)
+		       u64 size)
 {
 	struct ttm_resource_manager *man;
 	struct ttm_range_manager *rman;
@@ -191,9 +191,9 @@ int ttm_range_man_init_nocheck(struct ttm_device *bdev,
 
 	man->func = &ttm_range_manager_func;
 
-	ttm_resource_manager_init(man, bdev, p_size);
+	ttm_resource_manager_init(man, bdev, size);
 
-	drm_mm_init(&rman->mm, 0, p_size);
+	drm_mm_init(&rman->mm, 0, size);
 	spin_lock_init(&rman->lock);
 
 	ttm_set_driver_manager(bdev, type, &rman->manager);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index 9ad28346aff7..4926e7c73e75 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -700,7 +700,7 @@ static int vmw_vram_manager_init(struct vmw_private *dev_priv)
 {
 	int ret;
 	ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false,
-				 dev_priv->vram_size >> PAGE_SHIFT);
+				 dev_priv->vram_size);
 	ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false);
 	return ret;
 }
diff --git a/include/drm/ttm/ttm_range_manager.h b/include/drm/ttm/ttm_range_manager.h
index 7963b957e9ef..05bffded1b53 100644
--- a/include/drm/ttm/ttm_range_manager.h
+++ b/include/drm/ttm/ttm_range_manager.h
@@ -36,15 +36,15 @@ to_ttm_range_mgr_node(struct ttm_resource *res)
 
 int ttm_range_man_init_nocheck(struct ttm_device *bdev,
 		       unsigned type, bool use_tt,
-		       unsigned long p_size);
+		       u64 size);
 int ttm_range_man_fini_nocheck(struct ttm_device *bdev,
 		       unsigned type);
 static __always_inline int ttm_range_man_init(struct ttm_device *bdev,
 		       unsigned int type, bool use_tt,
-		       unsigned long p_size)
+		       u64 size)
 {
 	BUILD_BUG_ON(__builtin_constant_p(type) && type >= TTM_NUM_MEM_TYPES);
-	return ttm_range_man_init_nocheck(bdev, type, use_tt, p_size);
+	return ttm_range_man_init_nocheck(bdev, type, use_tt, size);
 }
 
 static __always_inline int ttm_range_man_fini(struct ttm_device *bdev,
-- 
2.32.0

[Nouveau] [PATCH 5/6] drm/ttm: Change the meaning of the fields in the drm_mm_nodes structure from pfn to bytes

[Somalapuram Amaranath]

Change the ttm_range_man_alloc() allocation from pages to size in bytes.
Fix the dependent drm_mm_nodes start and size from pages to bytes.

Signed-off-by: Somalapuram Amaranath <Amaranath.Somalapuram@amd.com>
---
 drivers/gpu/drm/i915/i915_scatterlist.c |  6 +++---
 drivers/gpu/drm/ttm/ttm_range_manager.c | 15 +++++++--------
 2 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_scatterlist.c b/drivers/gpu/drm/i915/i915_scatterlist.c
index 756289e43dff..7defda1219d0 100644
--- a/drivers/gpu/drm/i915/i915_scatterlist.c
+++ b/drivers/gpu/drm/i915/i915_scatterlist.c
@@ -94,7 +94,7 @@ struct i915_refct_sgt *i915_rsgt_from_mm_node(const struct drm_mm_node *node,
 	if (!rsgt)
 		return ERR_PTR(-ENOMEM);
 
-	i915_refct_sgt_init(rsgt, node->size << PAGE_SHIFT);
+	i915_refct_sgt_init(rsgt, node->size);
 	st = &rsgt->table;
 	/* restricted by sg_alloc_table */
 	if (WARN_ON(overflows_type(DIV_ROUND_UP_ULL(node->size, segment_pages),
@@ -110,8 +110,8 @@ struct i915_refct_sgt *i915_rsgt_from_mm_node(const struct drm_mm_node *node,
 	sg = st->sgl;
 	st->nents = 0;
 	prev_end = (resource_size_t)-1;
-	block_size = node->size << PAGE_SHIFT;
-	offset = node->start << PAGE_SHIFT;
+	block_size = node->size;
+	offset = node->start;
 
 	while (block_size) {
 		u64 len;
diff --git a/drivers/gpu/drm/ttm/ttm_range_manager.c b/drivers/gpu/drm/ttm/ttm_range_manager.c
index 62fddcc59f02..ff9962f7f81d 100644
--- a/drivers/gpu/drm/ttm/ttm_range_manager.c
+++ b/drivers/gpu/drm/ttm/ttm_range_manager.c
@@ -83,9 +83,10 @@ static int ttm_range_man_alloc(struct ttm_resource_manager *man,
 
 	spin_lock(&rman->lock);
 	ret = drm_mm_insert_node_in_range(mm, &node->mm_nodes[0],
-					  PFN_UP(node->base.size),
-					  bo->page_alignment, 0,
-					  place->fpfn, lpfn, mode);
+					  node->base.size,
+					  bo->page_alignment << PAGE_SHIFT, 0,
+					  place->fpfn << PAGE_SHIFT,
+					  lpfn << PAGE_SHIFT, mode);
 	spin_unlock(&rman->lock);
 
 	if (unlikely(ret)) {
@@ -119,11 +120,10 @@ static bool ttm_range_man_intersects(struct ttm_resource_manager *man,
 				     size_t size)
 {
 	struct drm_mm_node *node = &to_ttm_range_mgr_node(res)->mm_nodes[0];
-	u32 num_pages = PFN_UP(size);
 
 	/* Don't evict BOs outside of the requested placement range */
-	if (place->fpfn >= (node->start + num_pages) ||
-	    (place->lpfn && place->lpfn <= node->start))
+	if ((place->fpfn << PAGE_SHIFT) >= (node->start + size) ||
+	    (place->lpfn && (place->lpfn << PAGE_SHIFT) <= node->start))
 		return false;
 
 	return true;
@@ -135,10 +135,9 @@ static bool ttm_range_man_compatible(struct ttm_resource_manager *man,
 				     size_t size)
 {
 	struct drm_mm_node *node = &to_ttm_range_mgr_node(res)->mm_nodes[0];
-	u32 num_pages = PFN_UP(size);
 
 	if (node->start < place->fpfn ||
-	    (place->lpfn && (node->start + num_pages) > place->lpfn))
+	    (place->lpfn && (node->start + size) > place->lpfn << PAGE_SHIFT))
 		return false;
 
 	return true;
-- 
2.32.0

[Nouveau] [PATCH 6/6] drm/amdgpu: Cleanup the GDS, GWS and OA allocations

[Somalapuram Amaranath]

Change the size of GDS, GWS and OA from pages to bytes.
The initialized gds_size, gws_size and oa_size in bytes,
remove PAGE_SHIFT in amdgpu_ttm_init_on_chip().
:
Signed-off-by: Somalapuram Amaranath <Amaranath.Somalapuram@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c    | 12 ++++++------
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c |  3 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c    |  3 +--
 3 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index c3d9d75143f4..4641b25956fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -142,16 +142,16 @@ void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds,
 			      struct amdgpu_bo *gws, struct amdgpu_bo *oa)
 {
 	if (gds) {
-		job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
-		job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;
+		job->gds_base = amdgpu_bo_gpu_offset(gds);
+		job->gds_size = amdgpu_bo_size(gds);
 	}
 	if (gws) {
-		job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT;
-		job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT;
+		job->gws_base = amdgpu_bo_gpu_offset(gws);
+		job->gws_size = amdgpu_bo_size(gws);
 	}
 	if (oa) {
-		job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT;
-		job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT;
+		job->oa_base = amdgpu_bo_gpu_offset(oa);
+		job->oa_size = amdgpu_bo_size(oa);
 	}
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index f5d5eee09cea..9285037d6d88 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -541,12 +541,11 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
 	if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
 		/* GWS and OA don't need any alignment. */
 		page_align = bp->byte_align;
-		size <<= PAGE_SHIFT;
 
 	} else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) {
 		/* Both size and alignment must be a multiple of 4. */
 		page_align = ALIGN(bp->byte_align, 4);
-		size = ALIGN(size, 4) << PAGE_SHIFT;
+		size = ALIGN(size, 4);
 	} else {
 		/* Memory should be aligned at least to a page size. */
 		page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index f0dabdfd3780..a8e444a31d8f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -77,8 +77,7 @@ static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
 				    unsigned int type,
 				    uint64_t size)
 {
-	return ttm_range_man_init(&adev->mman.bdev, type,
-				  false, size << PAGE_SHIFT);
+	return ttm_range_man_init(&adev->mman.bdev, type, false, size);
 }
 
 /**
-- 
2.32.0

Re: [Nouveau] [PATCH 2/6] drm/amdgpu: Remove TTM resource->start visible VRAM condition

[Christian König]

Am 08.02.23 um 10:01 schrieb Somalapuram Amaranath:
> Use amdgpu_bo_in_cpu_visible_vram() instead.
>
> Signed-off-by: Somalapuram Amaranath <Amaranath.Somalapuram@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 9 +++------
>   1 file changed, 3 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 981010de0a28..d835ee2131d2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -600,7 +600,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
>   
>   	if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
>   	    bo->tbo.resource->mem_type == TTM_PL_VRAM &&
> -	    bo->tbo.resource->start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
> +	    amdgpu_bo_in_cpu_visible_vram(bo))
>   		amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
>   					     ctx.bytes_moved);
>   	else
> @@ -1346,7 +1346,6 @@ vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
>   	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
>   	struct ttm_operation_ctx ctx = { false, false };
>   	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
> -	unsigned long offset;
>   	int r;
>   
>   	/* Remember that this BO was accessed by the CPU */
> @@ -1355,8 +1354,7 @@ vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
>   	if (bo->resource->mem_type != TTM_PL_VRAM)
>   		return 0;
>   
> -	offset = bo->resource->start << PAGE_SHIFT;
> -	if ((offset + bo->base.size) <= adev->gmc.visible_vram_size)
> +	if (amdgpu_bo_in_cpu_visible_vram(abo))
>   		return 0;
>   
>   	/* Can't move a pinned BO to visible VRAM */
> @@ -1378,10 +1376,9 @@ vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
>   	else if (unlikely(r))
>   		return VM_FAULT_SIGBUS;
>   
> -	offset = bo->resource->start << PAGE_SHIFT;
>   	/* this should never happen */
>   	if (bo->resource->mem_type == TTM_PL_VRAM &&
> -	    (offset + bo->base.size) > adev->gmc.visible_vram_size)
> +	    amdgpu_bo_in_cpu_visible_vram(abo))

This check needs to be inversed. E.g. we return the error if the BO is 
not in visible VRAM.

Apart from that the patch looks good to me.

Regards,
Christian.

>   		return VM_FAULT_SIGBUS;
>   
>   	ttm_bo_move_to_lru_tail_unlocked(bo);

Re: [Nouveau] [PATCH 3/6] drm/ttm: Change the meaning of resource->start from pfn to bytes

[Christian König]

That finally starts to look sane. I'm going to make a few more 
adjustments and then send this out.

Christian.

Am 08.02.23 um 10:01 schrieb Somalapuram Amaranath:
> Change resource->start from pfn to bytes to
> allow allocating objects smaller than a page.
> Change all DRM drivers using ttm_resource start and size pfn to bytes.
> Change amdgpu_res_first() cur->start, cur->size from pfn to bytes.
> Replacing ttm_resource resource->start field with cursor.start.
> Change amdgpu_gtt_mgr_new() allocation from pfn to bytes.
>
> Signed-off-by: Somalapuram Amaranath <Amaranath.Somalapuram@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c         | 13 +++++++------
>   drivers/gpu/drm/amd/amdgpu/amdgpu_object.c          |  4 +++-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h      |  8 ++++----
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c             | 10 +++++++---
>   .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c   |  6 +++++-
>   drivers/gpu/drm/drm_gem_vram_helper.c               |  2 +-
>   drivers/gpu/drm/nouveau/nouveau_bo.c                | 13 ++++++-------
>   drivers/gpu/drm/nouveau/nouveau_bo0039.c            |  4 ++--
>   drivers/gpu/drm/nouveau/nouveau_mem.c               | 10 +++++-----
>   drivers/gpu/drm/nouveau/nouveau_ttm.c               |  2 +-
>   drivers/gpu/drm/nouveau/nv17_fence.c                |  2 +-
>   drivers/gpu/drm/nouveau/nv50_fence.c                |  2 +-
>   drivers/gpu/drm/qxl/qxl_drv.h                       |  2 +-
>   drivers/gpu/drm/qxl/qxl_object.c                    |  2 +-
>   drivers/gpu/drm/qxl/qxl_ttm.c                       |  5 ++---
>   drivers/gpu/drm/radeon/radeon_object.c              |  6 +++---
>   drivers/gpu/drm/radeon/radeon_object.h              |  2 +-
>   drivers/gpu/drm/radeon/radeon_ttm.c                 | 13 ++++++-------
>   drivers/gpu/drm/radeon/radeon_vm.c                  |  2 +-
>   drivers/gpu/drm/vmwgfx/vmwgfx_bo.c                  |  4 ++--
>   drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c                 |  2 +-
>   drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c             |  2 +-
>   drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c          |  3 +--
>   23 files changed, 63 insertions(+), 56 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> index 44367f03316f..a1fbfc5984d8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> @@ -116,7 +116,6 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager *man,
>   			      struct ttm_resource **res)
>   {
>   	struct amdgpu_gtt_mgr *mgr = to_gtt_mgr(man);
> -	uint32_t num_pages = PFN_UP(tbo->base.size);
>   	struct ttm_range_mgr_node *node;
>   	int r;
>   
> @@ -134,8 +133,10 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager *man,
>   	if (place->lpfn) {
>   		spin_lock(&mgr->lock);
>   		r = drm_mm_insert_node_in_range(&mgr->mm, &node->mm_nodes[0],
> -						num_pages, tbo->page_alignment,
> -						0, place->fpfn, place->lpfn,
> +						tbo->base.size,
> +						tbo->page_alignment << PAGE_SHIFT, 0,
> +						place->fpfn << PAGE_SHIFT,
> +						place->lpfn << PAGE_SHIFT,
>   						DRM_MM_INSERT_BEST);
>   		spin_unlock(&mgr->lock);
>   		if (unlikely(r))
> @@ -144,7 +145,7 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager *man,
>   		node->base.start = node->mm_nodes[0].start;
>   	} else {
>   		node->mm_nodes[0].start = 0;
> -		node->mm_nodes[0].size = PFN_UP(node->base.size);
> +		node->mm_nodes[0].size = node->base.size;
>   		node->base.start = AMDGPU_BO_INVALID_OFFSET;
>   	}
>   
> @@ -285,8 +286,8 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size)
>   
>   	ttm_resource_manager_init(man, &adev->mman.bdev, gtt_size);
>   
> -	start = AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS;
> -	size = (adev->gmc.gart_size >> PAGE_SHIFT) - start;
> +	start = (AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS) << PAGE_SHIFT;
> +	size = adev->gmc.gart_size - start;
>   	drm_mm_init(&mgr->mm, start, size);
>   	spin_lock_init(&mgr->lock);
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index d835ee2131d2..f5d5eee09cea 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -1488,9 +1488,11 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
>   u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
>   {
>   	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> +	struct amdgpu_res_cursor cursor;
>   	uint64_t offset;
>   
> -	offset = (bo->tbo.resource->start << PAGE_SHIFT) +
> +	amdgpu_res_first(bo->tbo.resource, 0, bo->tbo.resource->size, &cursor);
> +	offset = cursor.start +
>   		 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type);
>   
>   	return amdgpu_gmc_sign_extend(offset);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
> index 5c4f93ee0c57..5c78f0b09351 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h
> @@ -94,8 +94,8 @@ static inline void amdgpu_res_first(struct ttm_resource *res,
>   		while (start >= node->size << PAGE_SHIFT)
>   			start -= node++->size << PAGE_SHIFT;
>   
> -		cur->start = (node->start << PAGE_SHIFT) + start;
> -		cur->size = min((node->size << PAGE_SHIFT) - start, size);
> +		cur->start = node->start + start;
> +		cur->size = min(node->size - start, size);
>   		cur->remaining = size;
>   		cur->node = node;
>   		break;
> @@ -155,8 +155,8 @@ static inline void amdgpu_res_next(struct amdgpu_res_cursor *cur, uint64_t size)
>   		node = cur->node;
>   
>   		cur->node = ++node;
> -		cur->start = node->start << PAGE_SHIFT;
> -		cur->size = min(node->size << PAGE_SHIFT, cur->remaining);
> +		cur->start = node->start;
> +		cur->size = min(node->size, cur->remaining);
>   		break;
>   	default:
>   		return;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 2cd081cbf706..6b270d4662a3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -845,6 +845,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
>   {
>   	struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
>   	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(ttm);
> +	struct amdgpu_res_cursor cursor;
>   	uint64_t flags;
>   	int r;
>   
> @@ -892,7 +893,8 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
>   	flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
>   
>   	/* bind pages into GART page tables */
> -	gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
> +	amdgpu_res_first(bo_mem, 0, bo_mem->size, &cursor);
> +	gtt->offset = cursor.start;
>   	amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
>   			 gtt->ttm.dma_address, flags);
>   	gtt->bound = true;
> @@ -912,6 +914,7 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
>   	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
>   	struct ttm_operation_ctx ctx = { false, false };
>   	struct amdgpu_ttm_tt *gtt = ttm_to_amdgpu_ttm_tt(bo->ttm);
> +	struct amdgpu_res_cursor cursor;
>   	struct ttm_placement placement;
>   	struct ttm_place placements;
>   	struct ttm_resource *tmp;
> @@ -923,7 +926,7 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
>   
>   	addr = amdgpu_gmc_agp_addr(bo);
>   	if (addr != AMDGPU_BO_INVALID_OFFSET) {
> -		bo->resource->start = addr >> PAGE_SHIFT;
> +		bo->resource->start = addr;
>   		return 0;
>   	}
>   
> @@ -945,7 +948,8 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
>   	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp);
>   
>   	/* Bind pages */
> -	gtt->offset = (u64)tmp->start << PAGE_SHIFT;
> +	amdgpu_res_first(tmp, 0, tmp->size, &cursor);
> +	gtt->offset = cursor.start;
>   	amdgpu_ttm_gart_bind(adev, bo, flags);
>   	amdgpu_gart_invalidate_tlb(adev);
>   	ttm_resource_free(bo, &bo->resource);
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> index c06ada0844ba..9114393d2ee6 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> @@ -200,8 +200,12 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q,
>   	queue_input.wptr_addr = (uint64_t)q->properties.write_ptr;
>   
>   	if (q->wptr_bo) {
> +		struct amdgpu_res_cursor cursor;
> +
>   		wptr_addr_off = (uint64_t)q->properties.write_ptr & (PAGE_SIZE - 1);
> -		queue_input.wptr_mc_addr = ((uint64_t)q->wptr_bo->tbo.resource->start << PAGE_SHIFT) + wptr_addr_off;
> +		amdgpu_res_first(q->wptr_bo->tbo.resource, 0,
> +				 q->wptr_bo->tbo.resource->size, &cursor);
> +		queue_input.wptr_mc_addr = cursor.start + wptr_addr_off;
>   	}
>   
>   	queue_input.is_kfd_process = 1;
> diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c b/drivers/gpu/drm/drm_gem_vram_helper.c
> index d40b3edb52d0..e7be562790de 100644
> --- a/drivers/gpu/drm/drm_gem_vram_helper.c
> +++ b/drivers/gpu/drm/drm_gem_vram_helper.c
> @@ -275,7 +275,7 @@ s64 drm_gem_vram_offset(struct drm_gem_vram_object *gbo)
>   {
>   	if (WARN_ON_ONCE(!gbo->bo.pin_count))
>   		return (s64)-ENODEV;
> -	return drm_gem_vram_pg_offset(gbo) << PAGE_SHIFT;
> +	return drm_gem_vram_pg_offset(gbo);
>   }
>   EXPORT_SYMBOL(drm_gem_vram_offset);
>   
> diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
> index c2ec91cc845d..89fada6c2e11 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_bo.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
> @@ -946,7 +946,7 @@ static void nouveau_bo_move_ntfy(struct ttm_buffer_object *bo,
>   	}
>   
>   	if (new_reg)
> -		nvbo->offset = (new_reg->start << PAGE_SHIFT);
> +		nvbo->offset = new_reg->start;
>   
>   }
>   
> @@ -957,7 +957,7 @@ nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg,
>   	struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
>   	struct drm_device *dev = drm->dev;
>   	struct nouveau_bo *nvbo = nouveau_bo(bo);
> -	u64 offset = new_reg->start << PAGE_SHIFT;
> +	u64 offset = new_reg->start;
>   
>   	*new_tile = NULL;
>   	if (new_reg->mem_type != TTM_PL_VRAM)
> @@ -1118,8 +1118,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *reg)
>   	case TTM_PL_TT:
>   #if IS_ENABLED(CONFIG_AGP)
>   		if (drm->agp.bridge) {
> -			reg->bus.offset = (reg->start << PAGE_SHIFT) +
> -				drm->agp.base;
> +			reg->bus.offset = reg->start + drm->agp.base;
>   			reg->bus.is_iomem = !drm->agp.cma;
>   			reg->bus.caching = ttm_write_combined;
>   		}
> @@ -1132,7 +1131,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *reg)
>   		}
>   		fallthrough;	/* tiled memory */
>   	case TTM_PL_VRAM:
> -		reg->bus.offset = (reg->start << PAGE_SHIFT) +
> +		reg->bus.offset = reg->start +
>   			device->func->resource_addr(device, 1);
>   		reg->bus.is_iomem = true;
>   
> @@ -1222,7 +1221,7 @@ vm_fault_t nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
>   	struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
>   	struct nouveau_bo *nvbo = nouveau_bo(bo);
>   	struct nvkm_device *device = nvxx_device(&drm->client.device);
> -	u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
> +	u32 mappable = device->func->resource_size(device, 1);
>   	int i, ret;
>   
>   	/* as long as the bo isn't in vram, and isn't tiled, we've got
> @@ -1241,7 +1240,7 @@ vm_fault_t nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
>   	} else {
>   		/* make sure bo is in mappable vram */
>   		if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
> -		    bo->resource->start + PFN_UP(bo->resource->size) < mappable)
> +		    bo->resource->start + bo->resource->size < mappable)
>   			return 0;
>   
>   		for (i = 0; i < nvbo->placement.num_placement; ++i) {
> diff --git a/drivers/gpu/drm/nouveau/nouveau_bo0039.c b/drivers/gpu/drm/nouveau/nouveau_bo0039.c
> index e2ce44adaa5c..41197312f82f 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_bo0039.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_bo0039.c
> @@ -49,9 +49,9 @@ nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
>   {
>   	struct nvif_push *push = chan->chan.push;
>   	u32 src_ctxdma = nouveau_bo_mem_ctxdma(bo, chan, old_reg);
> -	u32 src_offset = old_reg->start << PAGE_SHIFT;
> +	u32 src_offset = old_reg->start;
>   	u32 dst_ctxdma = nouveau_bo_mem_ctxdma(bo, chan, new_reg);
> -	u32 dst_offset = new_reg->start << PAGE_SHIFT;
> +	u32 dst_offset = new_reg->start;
>   	u32 page_count = PFN_UP(new_reg->size);
>   	int ret;
>   
> diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
> index 25f31d5169e5..d31cc3b069d8 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_mem.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
> @@ -158,7 +158,7 @@ nouveau_mem_vram(struct ttm_resource *reg, bool contig, u8 page)
>   	}
>   	mutex_unlock(&drm->master.lock);
>   
> -	reg->start = mem->mem.addr >> PAGE_SHIFT;
> +	reg->start = mem->mem.addr;
>   	return ret;
>   }
>   
> @@ -197,8 +197,8 @@ nouveau_mem_intersects(struct ttm_resource *res,
>   	u32 num_pages = PFN_UP(size);
>   
>   	/* Don't evict BOs outside of the requested placement range */
> -	if (place->fpfn >= (res->start + num_pages) ||
> -	    (place->lpfn && place->lpfn <= res->start))
> +	if (place->fpfn >= ((res->start >> PAGE_SHIFT) + num_pages) ||
> +	    (place->lpfn && place->lpfn <= (res->start >> PAGE_SHIFT)))
>   		return false;
>   
>   	return true;
> @@ -211,8 +211,8 @@ nouveau_mem_compatible(struct ttm_resource *res,
>   {
>   	u32 num_pages = PFN_UP(size);
>   
> -	if (res->start < place->fpfn ||
> -	    (place->lpfn && (res->start + num_pages) > place->lpfn))
> +	if ((res->start >> PAGE_SHIFT) < place->fpfn ||
> +	    (place->lpfn && ((res->start >> PAGE_SHIFT) + num_pages) > place->lpfn))
>   		return false;
>   
>   	return true;
> diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c
> index 1469a88910e4..2127b98e033a 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_ttm.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c
> @@ -145,7 +145,7 @@ nv04_gart_manager_new(struct ttm_resource_manager *man,
>   		return ret;
>   	}
>   
> -	(*res)->start = mem->vma[0].addr >> PAGE_SHIFT;
> +	(*res)->start = mem->vma[0].addr;
>   	return 0;
>   }
>   
> diff --git a/drivers/gpu/drm/nouveau/nv17_fence.c b/drivers/gpu/drm/nouveau/nv17_fence.c
> index 07c2e0878c24..b6567e5f769c 100644
> --- a/drivers/gpu/drm/nouveau/nv17_fence.c
> +++ b/drivers/gpu/drm/nouveau/nv17_fence.c
> @@ -79,7 +79,7 @@ nv17_fence_context_new(struct nouveau_channel *chan)
>   	struct nv10_fence_priv *priv = chan->drm->fence;
>   	struct ttm_resource *reg = priv->bo->bo.resource;
>   	struct nv10_fence_chan *fctx;
> -	u32 start = reg->start * PAGE_SIZE;
> +	u32 start = reg->start;
>   	u32 limit = start + priv->bo->bo.base.size - 1;
>   	int ret = 0;
>   
> diff --git a/drivers/gpu/drm/nouveau/nv50_fence.c b/drivers/gpu/drm/nouveau/nv50_fence.c
> index ea1e1f480bfe..c3f1df834bb9 100644
> --- a/drivers/gpu/drm/nouveau/nv50_fence.c
> +++ b/drivers/gpu/drm/nouveau/nv50_fence.c
> @@ -38,7 +38,7 @@ nv50_fence_context_new(struct nouveau_channel *chan)
>   	struct nv10_fence_priv *priv = chan->drm->fence;
>   	struct nv10_fence_chan *fctx;
>   	struct ttm_resource *reg = priv->bo->bo.resource;
> -	u32 start = reg->start * PAGE_SIZE;
> +	u32 start = reg->start;
>   	u32 limit = start + priv->bo->bo.base.size - 1;
>   	int ret;
>   
> diff --git a/drivers/gpu/drm/qxl/qxl_drv.h b/drivers/gpu/drm/qxl/qxl_drv.h
> index ea993d7162e8..994996e6a623 100644
> --- a/drivers/gpu/drm/qxl/qxl_drv.h
> +++ b/drivers/gpu/drm/qxl/qxl_drv.h
> @@ -289,7 +289,7 @@ qxl_bo_physical_address(struct qxl_device *qdev, struct qxl_bo *bo,
>   
>          /* TODO - need to hold one of the locks to read bo->tbo.resource->start */
>   
> -	return slot->high_bits | ((bo->tbo.resource->start << PAGE_SHIFT) + offset);
> +	return slot->high_bits | (bo->tbo.resource->start + offset);
>   }
>   
>   /* qxl_display.c */
> diff --git a/drivers/gpu/drm/qxl/qxl_object.c b/drivers/gpu/drm/qxl/qxl_object.c
> index 06a58dad5f5c..657b9995f4f6 100644
> --- a/drivers/gpu/drm/qxl/qxl_object.c
> +++ b/drivers/gpu/drm/qxl/qxl_object.c
> @@ -220,7 +220,7 @@ void *qxl_bo_kmap_atomic_page(struct qxl_device *qdev,
>   	else
>   		goto fallback;
>   
> -	offset = bo->tbo.resource->start << PAGE_SHIFT;
> +	offset = bo->tbo.resource->start;
>   	return io_mapping_map_atomic_wc(map, offset + page_offset);
>   fallback:
>   	if (bo->kptr) {
> diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c
> index a92a5b0d4c25..31f96c7d89b4 100644
> --- a/drivers/gpu/drm/qxl/qxl_ttm.c
> +++ b/drivers/gpu/drm/qxl/qxl_ttm.c
> @@ -81,13 +81,12 @@ int qxl_ttm_io_mem_reserve(struct ttm_device *bdev,
>   		return 0;
>   	case TTM_PL_VRAM:
>   		mem->bus.is_iomem = true;
> -		mem->bus.offset = (mem->start << PAGE_SHIFT) + qdev->vram_base;
> +		mem->bus.offset = mem->start + qdev->vram_base;
>   		mem->bus.caching = ttm_write_combined;
>   		break;
>   	case TTM_PL_PRIV:
>   		mem->bus.is_iomem = true;
> -		mem->bus.offset = (mem->start << PAGE_SHIFT) +
> -			qdev->surfaceram_base;
> +		mem->bus.offset = mem->start + qdev->surfaceram_base;
>   		mem->bus.caching = ttm_write_combined;
>   		break;
>   	default:
> diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
> index 10c0fbd9d2b4..83d50c72aeeb 100644
> --- a/drivers/gpu/drm/radeon/radeon_object.c
> +++ b/drivers/gpu/drm/radeon/radeon_object.c
> @@ -588,7 +588,7 @@ int radeon_bo_get_surface_reg(struct radeon_bo *bo)
>   
>   out:
>   	radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
> -			       bo->tbo.resource->start << PAGE_SHIFT,
> +			       bo->tbo.resource->start,
>   			       bo->tbo.base.size);
>   	return 0;
>   }
> @@ -738,7 +738,7 @@ vm_fault_t radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
>   		return 0;
>   
>   	size = bo->resource->size;
> -	offset = bo->resource->start << PAGE_SHIFT;
> +	offset = bo->resource->start;
>   	if ((offset + size) <= rdev->mc.visible_vram_size)
>   		return 0;
>   
> @@ -760,7 +760,7 @@ vm_fault_t radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
>   		radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
>   		r = ttm_bo_validate(bo, &rbo->placement, &ctx);
>   	} else if (likely(!r)) {
> -		offset = bo->resource->start << PAGE_SHIFT;
> +		offset = bo->resource->start;
>   		/* this should never happen */
>   		if ((offset + size) > rdev->mc.visible_vram_size)
>   			return VM_FAULT_SIGBUS;
> diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h
> index 0a6ef49e990a..6e0002e08c57 100644
> --- a/drivers/gpu/drm/radeon/radeon_object.h
> +++ b/drivers/gpu/drm/radeon/radeon_object.h
> @@ -104,7 +104,7 @@ static inline u64 radeon_bo_gpu_offset(struct radeon_bo *bo)
>   		break;
>   	}
>   
> -	return (bo->tbo.resource->start << PAGE_SHIFT) + start;
> +	return bo->tbo.resource->start + start;
>   }
>   
>   static inline unsigned long radeon_bo_size(struct radeon_bo *bo)
> diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
> index 67075c85f847..777d38b211d2 100644
> --- a/drivers/gpu/drm/radeon/radeon_ttm.c
> +++ b/drivers/gpu/drm/radeon/radeon_ttm.c
> @@ -104,7 +104,7 @@ static void radeon_evict_flags(struct ttm_buffer_object *bo,
>   		if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
>   			radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
>   		else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size &&
> -			 bo->resource->start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) {
> +			 bo->resource->start < rbo->rdev->mc.visible_vram_size) {
>   			unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
>   			int i;
>   
> @@ -149,8 +149,8 @@ static int radeon_move_blit(struct ttm_buffer_object *bo,
>   
>   	rdev = radeon_get_rdev(bo->bdev);
>   	ridx = radeon_copy_ring_index(rdev);
> -	old_start = (u64)old_mem->start << PAGE_SHIFT;
> -	new_start = (u64)new_mem->start << PAGE_SHIFT;
> +	old_start = (u64)old_mem->start;
> +	new_start = (u64)new_mem->start;
>   
>   	switch (old_mem->mem_type) {
>   	case TTM_PL_VRAM:
> @@ -274,15 +274,14 @@ static int radeon_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resourc
>   #if IS_ENABLED(CONFIG_AGP)
>   		if (rdev->flags & RADEON_IS_AGP) {
>   			/* RADEON_IS_AGP is set only if AGP is active */
> -			mem->bus.offset = (mem->start << PAGE_SHIFT) +
> -				rdev->mc.agp_base;
> +			mem->bus.offset = mem->start + rdev->mc.agp_base;
>   			mem->bus.is_iomem = !rdev->agp->cant_use_aperture;
>   			mem->bus.caching = ttm_write_combined;
>   		}
>   #endif
>   		break;
>   	case TTM_PL_VRAM:
> -		mem->bus.offset = mem->start << PAGE_SHIFT;
> +		mem->bus.offset = mem->start;
>   		/* check if it's visible */
>   		if ((mem->bus.offset + bus_size) > rdev->mc.visible_vram_size)
>   			return -EINVAL;
> @@ -443,7 +442,7 @@ static int radeon_ttm_backend_bind(struct ttm_device *bdev,
>   		flags &= ~RADEON_GART_PAGE_WRITE;
>   	}
>   
> -	gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
> +	gtt->offset = (unsigned long)bo_mem->start;
>   	if (!ttm->num_pages) {
>   		WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
>   		     ttm->num_pages, bo_mem, ttm);
> diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c
> index 987cabbf1318..27ba2f6c4ac5 100644
> --- a/drivers/gpu/drm/radeon/radeon_vm.c
> +++ b/drivers/gpu/drm/radeon/radeon_vm.c
> @@ -945,7 +945,7 @@ int radeon_vm_bo_update(struct radeon_device *rdev,
>   		bo_va->flags &= ~RADEON_VM_PAGE_WRITEABLE;
>   
>   	if (mem) {
> -		addr = (u64)mem->start << PAGE_SHIFT;
> +		addr = (u64)mem->start;
>   		if (mem->mem_type != TTM_PL_SYSTEM)
>   			bo_va->flags |= RADEON_VM_PAGE_VALID;
>   
> diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c b/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
> index 9bf1f9d2f9b6..f58af9753ca1 100644
> --- a/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
> +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
> @@ -200,7 +200,7 @@ int vmw_bo_pin_in_start_of_vram(struct vmw_private *dev_priv,
>   	 * that situation.
>   	 */
>   	if (bo->resource->mem_type == TTM_PL_VRAM &&
> -	    bo->resource->start < PFN_UP(bo->resource->size) &&
> +	    bo->resource->start < bo->resource->size &&
>   	    bo->resource->start > 0 &&
>   	    buf->base.pin_count == 0) {
>   		ctx.interruptible = false;
> @@ -263,7 +263,7 @@ void vmw_bo_get_guest_ptr(const struct ttm_buffer_object *bo,
>   {
>   	if (bo->resource->mem_type == TTM_PL_VRAM) {
>   		ptr->gmrId = SVGA_GMR_FRAMEBUFFER;
> -		ptr->offset = bo->resource->start << PAGE_SHIFT;
> +		ptr->offset = bo->resource->start;
>   	} else {
>   		ptr->gmrId = bo->resource->start;
>   		ptr->offset = 0;
> diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c b/drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c
> index 162dfeb1cc5a..4883f8fc71f2 100644
> --- a/drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c
> +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c
> @@ -584,7 +584,7 @@ static int vmw_cmd_emit_dummy_legacy_query(struct vmw_private *dev_priv,
>   
>   	if (bo->resource->mem_type == TTM_PL_VRAM) {
>   		cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER;
> -		cmd->body.guestResult.offset = bo->resource->start << PAGE_SHIFT;
> +		cmd->body.guestResult.offset = bo->resource->start;
>   	} else {
>   		cmd->body.guestResult.gmrId = bo->resource->start;
>   		cmd->body.guestResult.offset = 0;
> diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
> index 9359e8dfbac2..c882990ac361 100644
> --- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
> +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
> @@ -3755,7 +3755,7 @@ static void vmw_apply_relocations(struct vmw_sw_context *sw_context)
>   		bo = &reloc->vbo->base;
>   		switch (bo->resource->mem_type) {
>   		case TTM_PL_VRAM:
> -			reloc->location->offset += bo->resource->start << PAGE_SHIFT;
> +			reloc->location->offset += bo->resource->start;
>   			reloc->location->gmrId = SVGA_GMR_FRAMEBUFFER;
>   			break;
>   		case VMW_PL_GMR:
> diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
> index 856a352a72a6..3b3cb872858b 100644
> --- a/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
> +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
> @@ -543,8 +543,7 @@ static int vmw_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *
>   	case VMW_PL_MOB:
>   		return 0;
>   	case TTM_PL_VRAM:
> -		mem->bus.offset = (mem->start << PAGE_SHIFT) +
> -			dev_priv->vram_start;
> +		mem->bus.offset = mem->start + dev_priv->vram_start;
>   		mem->bus.is_iomem = true;
>   		mem->bus.caching = ttm_cached;
>   		break;