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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2024 23:43:03.2210 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d4ce3dd1-aba8-4bed-4e9d-08dc5e6ef53d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003440.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4077 X-BeenThere: nouveau@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Nouveau development list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: nouveau-bounces@lists.freedesktop.org Sender: "Nouveau" - transition from "ioctl" interface Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/include/nvif/driverif.h | 4 +++ drivers/gpu/drm/nouveau/include/nvif/if0012.h | 14 -------- drivers/gpu/drm/nouveau/nvif/outp.c | 16 ++------- .../gpu/drm/nouveau/nvkm/engine/disp/uoutp.c | 33 ++++++++++--------- 4 files changed, 25 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/nouveau/include/nvif/driverif.h b/drivers/gpu/drm/nouveau/include/nvif/driverif.h index 9395ddad65bf..2660f37c5443 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/driverif.h +++ b/drivers/gpu/drm/nouveau/include/nvif/driverif.h @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: MIT */ #ifndef __NVIF_DRIVERIF_H__ #define __NVIF_DRIVERIF_H__ +#include + struct nvif_event_priv; struct nvif_client_priv; struct nvif_device_priv; @@ -334,6 +336,8 @@ struct nvif_outp_impl { int (*aux_pwr)(struct nvif_outp_priv *, bool enable); int (*aux_xfer)(struct nvif_outp_priv *, u8 type, u32 addr, u8 *data, u8 *size); int (*rates)(struct nvif_outp_priv *, struct nvif_outp_dp_rate *, u8 rates); + int (*train)(struct nvif_outp_priv *, u8 dpcd[DP_RECEIVER_CAP_SIZE], u8 lttprs, + u8 link_nr, u32 link_bw, bool mst, bool post_lt_adj, bool retrain); } dp; }; diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0012.h b/drivers/gpu/drm/nouveau/include/nvif/if0012.h index 327ff9aa3ae0..5db1f718e82c 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/if0012.h +++ b/drivers/gpu/drm/nouveau/include/nvif/if0012.h @@ -4,26 +4,12 @@ #include -#define NVIF_OUTP_V0_DP_TRAIN 0x73 #define NVIF_OUTP_V0_DP_DRIVE 0x74 #define NVIF_OUTP_V0_DP_SST 0x75 #define NVIF_OUTP_V0_DP_MST_ID_GET 0x76 #define NVIF_OUTP_V0_DP_MST_ID_PUT 0x77 #define NVIF_OUTP_V0_DP_MST_VCPI 0x78 -union nvif_outp_dp_train_args { - struct nvif_outp_dp_train_v0 { - __u8 version; - __u8 retrain; - __u8 mst; - __u8 lttprs; - __u8 post_lt_adj; - __u8 link_nr; - __u32 link_bw; - __u8 dpcd[DP_RECEIVER_CAP_SIZE]; - } v0; -}; - union nvif_outp_dp_drive_args { struct nvif_outp_dp_drive_v0 { __u8 version; diff --git a/drivers/gpu/drm/nouveau/nvif/outp.c b/drivers/gpu/drm/nouveau/nvif/outp.c index 68af891505d1..f20846a7f487 100644 --- a/drivers/gpu/drm/nouveau/nvif/outp.c +++ b/drivers/gpu/drm/nouveau/nvif/outp.c @@ -113,23 +113,13 @@ int nvif_outp_dp_train(struct nvif_outp *outp, u8 dpcd[DP_RECEIVER_CAP_SIZE], u8 lttprs, u8 link_nr, u32 link_bw, bool mst, bool post_lt_adj, bool retrain) { - struct nvif_outp_dp_train_v0 args; int ret; - args.version = 0; - args.retrain = retrain; - args.mst = mst; - args.lttprs = lttprs; - args.post_lt_adj = post_lt_adj; - args.link_nr = link_nr; - args.link_bw = link_bw; - memcpy(args.dpcd, dpcd, sizeof(args.dpcd)); - - ret = nvif_object_mthd(&outp->object, NVIF_OUTP_V0_DP_TRAIN, &args, sizeof(args)); + ret = outp->impl->dp.train(outp->priv, dpcd, lttprs, link_nr, link_bw, mst, + post_lt_adj, retrain); NVIF_ERRON(ret, &outp->object, "[DP_TRAIN retrain:%d mst:%d lttprs:%d post_lt_adj:%d nr:%d bw:%d]", - args.retrain, args.mst, args.lttprs, args.post_lt_adj, args.link_nr, - args.link_bw); + retrain, mst, lttprs, post_lt_adj, link_nr, link_bw); return ret; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c index 00b66d400f68..673c8c10c782 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c @@ -136,25 +136,28 @@ nvkm_uoutp_mthd_dp_drive(struct nvkm_outp *outp, void *argv, u32 argc) } static int -nvkm_uoutp_mthd_dp_train(struct nvkm_outp *outp, void *argv, u32 argc) +nvkm_uoutp_dp_train(struct nvif_outp_priv *uoutp, u8 dpcd[DP_RECEIVER_CAP_SIZE], u8 lttprs, + u8 link_nr, u32 link_bw, bool mst, bool post_lt_adj, bool retrain) { - union nvif_outp_dp_train_args *args = argv; + struct nvkm_outp *outp = uoutp->outp; + int ret; - if (argc != sizeof(args->v0) || args->v0.version != 0) - return -ENOSYS; - if (!outp->func->dp.train) - return -EINVAL; + ret = nvkm_uoutp_lock_acquired(uoutp); + if (ret) + return ret; - if (!args->v0.retrain) { - memcpy(outp->dp.dpcd, args->v0.dpcd, sizeof(outp->dp.dpcd)); - outp->dp.lttprs = args->v0.lttprs; - outp->dp.lt.nr = args->v0.link_nr; - outp->dp.lt.bw = args->v0.link_bw / 27000; - outp->dp.lt.mst = args->v0.mst; - outp->dp.lt.post_adj = args->v0.post_lt_adj; + if (!retrain) { + memcpy(outp->dp.dpcd, dpcd, sizeof(outp->dp.dpcd)); + outp->dp.lttprs = lttprs; + outp->dp.lt.nr = link_nr; + outp->dp.lt.bw = link_bw / 27000; + outp->dp.lt.mst = mst; + outp->dp.lt.post_adj = post_lt_adj; } - return outp->func->dp.train(outp, args->v0.retrain); + ret = outp->func->dp.train(outp, retrain); + nvkm_uoutp_unlock(uoutp); + return ret; } static int @@ -545,7 +548,6 @@ static int nvkm_uoutp_mthd_acquired(struct nvkm_outp *outp, u32 mthd, void *argv, u32 argc) { switch (mthd) { - case NVIF_OUTP_V0_DP_TRAIN : return nvkm_uoutp_mthd_dp_train (outp, argv, argc); case NVIF_OUTP_V0_DP_DRIVE : return nvkm_uoutp_mthd_dp_drive (outp, argv, argc); case NVIF_OUTP_V0_DP_SST : return nvkm_uoutp_mthd_dp_sst (outp, argv, argc); case NVIF_OUTP_V0_DP_MST_ID_GET: return nvkm_uoutp_mthd_dp_mst_id_get(outp, argv, argc); @@ -685,6 +687,7 @@ nvkm_uoutp_new(struct nvkm_disp *disp, u8 id, const struct nvif_outp_impl **pimp uoutp->impl.dp.aux_pwr = nvkm_uoutp_dp_aux_pwr; uoutp->impl.dp.aux_xfer = nvkm_uoutp_dp_aux_xfer; uoutp->impl.dp.rates = nvkm_uoutp_dp_rates; + uoutp->impl.dp.train = nvkm_uoutp_dp_train; break; default: WARN_ON(1); -- 2.41.0