From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2065.outbound.protection.outlook.com. [40.107.92.65]) by gmr-mx.google.com with ESMTPS id bj28si470534oib.2.2021.12.12.15.28.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 12 Dec 2021 15:28:04 -0800 (PST) Date: Sun, 12 Dec 2021 19:27:58 -0400 From: Jason Gunthorpe Subject: Re: [patch 21/32] NTB/msi: Convert to msi_on_each_desc() Message-ID: <20211212232758.GL6385@nvidia.com> References: <87k0go8432.ffs@tglx> <878rx480fk.ffs@tglx> <87sfv2yy19.ffs@tglx> <20211209162129.GS6385@nvidia.com> <878rwtzfh1.ffs@tglx> <20211209205835.GZ6385@nvidia.com> <3f6d4bd7-8b60-1976-73a4-f5ef7f3dbf27@nextfour.com> Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <3f6d4bd7-8b60-1976-73a4-f5ef7f3dbf27@nextfour.com> Return-Path: jgg@nvidia.com MIME-Version: 1.0 To: Mika =?utf-8?B?UGVudHRpbMOk?= Cc: "Tian, Kevin" , Thomas Gleixner , "Jiang, Dave" , Logan Gunthorpe , LKML , Bjorn Helgaas , Marc Zygnier , Alex Williamson , "Dey, Megha" , "Raj, Ashok" , "linux-pci@vger.kernel.org" , Greg Kroah-Hartman , Jon Mason , Allen Hubbe , "linux-ntb@googlegroups.com" , "linux-s390@vger.kernel.org" , Heiko Carstens , Christian Borntraeger , "x86@kernel.org" , Joerg Roedel , "iommu@lists.linux-foundation.org" List-ID: On Sun, Dec 12, 2021 at 08:44:46AM +0200, Mika Penttilä wrote: > > /* > > * The MSIX mappable capability informs that MSIX data of a BAR can be mmapped > > * which allows direct access to non-MSIX registers which happened to be within > > * the same system page. > > * > > * Even though the userspace gets direct access to the MSIX data, the existing > > * VFIO_DEVICE_SET_IRQS interface must still be used for MSIX configuration. > > */ > > #define VFIO_REGION_INFO_CAP_MSIX_MAPPABLE 3 > > > > IIRC this was introduced for PPC when a device has MSI-X in the same BAR as > > other MMIO registers. Trapping MSI-X leads to performance downgrade on > > accesses to adjacent registers. MSI-X can be mapped by userspace because > > PPC already uses a hypercall mechanism for interrupt. Though unclear about > > the detail it sounds a similar usage as proposed here. > > > > Thanks > > Kevin > > I see  VFIO_REGION_INFO_CAP_MSIX_MAPPABLE is always set so if msix table is > in its own bar, qemu never traps/emulates the access. It is some backwards compat, the kernel always sets it to indicate a new kernel, that doesn't mean qemu doesn't trap. As the comment says, ""VFIO_DEVICE_SET_IRQS interface must still be used for MSIX configuration"" so there is no way qemu can meet that without either trapping the MSI page or using a special hypercall (ppc) Jason