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From: Willie Thai <williethaitu@gmail.com>
To: openbmc@lists.ozlabs.org, joel@jms.id.au
Cc: willie <willie_thai@compal.com>
Subject: [PATCH] ARM: dts: aspeed: Add device tree for Liwu2 BMC
Date: Thu,  7 Jan 2021 11:41:49 +0800	[thread overview]
Message-ID: <1609990909-18189-1-git-send-email-willie_thai@compal.com> (raw)

From: willie <willie_thai@compal.com>

---
 arch/arm/boot/dts/Makefile                    |   3 +-
 arch/arm/boot/dts/aspeed-bmc-compal-liwu2.dts | 605 ++++++++++++++++++++++++++
 2 files changed, 607 insertions(+), 1 deletion(-)
 create mode 100755 arch/arm/boot/dts/aspeed-bmc-compal-liwu2.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5a14adc..8ccb5d3 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1381,4 +1381,5 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
 	aspeed-bmc-opp-zaius.dtb \
 	aspeed-bmc-portwell-neptune.dtb \
 	aspeed-bmc-quanta-q71l.dtb \
-	aspeed-bmc-supermicro-x11spi.dtb
+	aspeed-bmc-supermicro-x11spi.dtb \
+	aspeed-bmc-compal-liwu2.dtb
diff --git a/arch/arm/boot/dts/aspeed-bmc-compal-liwu2.dts b/arch/arm/boot/dts/aspeed-bmc-compal-liwu2.dts
new file mode 100755
index 0000000..5882b42
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-compal-liwu2.dts
@@ -0,0 +1,605 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+	model = "AST2500 liwu2";
+	compatible = "aspeed,ast2500";
+
+	aliases {
+		serial4 = &uart5;
+	};
+
+	chosen {
+		stdout-path = &uart5;
+		bootargs = "console=tty0 console=ttyS4,115200 earlyprintk";
+	};
+
+	memory@80000000 {
+		reg = <0x80000000 0x20000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		gfx_memory: framebuffer {
+			size = <0x01000000>;
+			alignment = <0x01000000>;
+			compatible = "shared-dma-pool";
+			reusable;
+		};
+	};
+
+	iio-hwmon {
+		compatible = "iio-hwmon";
+		io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+			      <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
+			      <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>,
+			      <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		LED_FAN0_FAULT {
+			label = "LED_FAN0_FAULT";
+			gpios = <&gpio ASPEED_GPIO(F, 4) GPIO_ACTIVE_LOW>;
+		};
+
+		LED_FAN1_FAULT {
+			label = "LED_FAN1_FAULT";
+			gpios = <&gpio ASPEED_GPIO(F, 5) GPIO_ACTIVE_LOW>;
+		};
+
+		LED_FAN2_FAULT {
+			label = "LED_FAN2_FAULT";
+			gpios = <&gpio ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>;
+		};
+
+		LED_FAN3_FAULT {
+			label = "LED_FAN3_FAULT";
+			gpios = <&gpio ASPEED_GPIO(H, 5) GPIO_ACTIVE_LOW>;
+		};
+
+		LED_FAN4_FAULT {
+			label = "LED_FAN4_FAULT";
+			gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>;
+		};
+
+		LED_FAN5_FAULT {
+			label = "LED_FAN5_FAULT";
+			gpios = <&gpio ASPEED_GPIO(H, 7) GPIO_ACTIVE_LOW>;
+		};
+
+		FP_LED_STATUS_AMBER_N {
+			label = "FP_LED_STATUS_AMBER_N";
+			gpios = <&gpio ASPEED_GPIO(S, 5) GPIO_ACTIVE_LOW>;
+		};
+
+		REAR_ID_LED_N {
+			label = "REAR_ID_LED_N";
+			gpios = <&gpio ASPEED_GPIO(S, 6) GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		poll-interval = <1000>;
+
+		FM_SYS_FAN0_PRSNT_D_N {
+			label = "FM_SYS_FAN0_PRSNT_D_N";
+			gpios = <&gpio ASPEED_GPIO(M, 0) GPIO_ACTIVE_LOW>;
+			linux,code = <ASPEED_GPIO(M, 0)>;
+		};
+
+		FM_SYS_FAN1_PRSNT_D_N {
+			label = "FM_SYS_FAN1_PRSNT_D_N";
+			gpios = <&gpio ASPEED_GPIO(M, 1) GPIO_ACTIVE_LOW>;
+			linux,code = <ASPEED_GPIO(M, 1)>;
+		};
+
+		FM_SYS_FAN2_PRSNT_D_N {
+			label = "FM_SYS_FAN2_PRSNT_D_N";
+			gpios = <&gpio ASPEED_GPIO(M, 2) GPIO_ACTIVE_LOW>;
+			linux,code = <ASPEED_GPIO(M, 2)>;
+		};
+
+		FM_SYS_FAN3_PRSNT_D_N {
+			label = "FM_SYS_FAN3_PRSNT_D_N";
+			gpios = <&gpio ASPEED_GPIO(M, 3) GPIO_ACTIVE_LOW>;
+			linux,code = <ASPEED_GPIO(M, 3)>;
+		};
+
+		FM_SYS_FAN4_PRSNT_D_N {
+			label = "FM_SYS_FAN4_PRSNT_D_N";
+			gpios = <&gpio ASPEED_GPIO(M, 4) GPIO_ACTIVE_LOW>;
+			linux,code = <ASPEED_GPIO(M, 4)>;
+		};
+
+		FM_SYS_FAN5_PRSNT_D_N {
+			label = "FM_SYS_FAN5_PRSNT_D_N";
+			gpios = <&gpio ASPEED_GPIO(M, 5) GPIO_ACTIVE_LOW>;
+			linux,code = <ASPEED_GPIO(M, 5)>;
+		};
+
+		FM_SYS_FAN6_PRSNT_D_N {
+			label = "FM_SYS_FAN6_PRSNT_D_N";
+			gpios = <&gpio ASPEED_GPIO(S, 7) GPIO_ACTIVE_LOW>;
+			linux,code = <ASPEED_GPIO(S, 7)>;
+		};
+
+		FM_SYS_FAN7_PRSNT_D_N {
+			label = "FM_SYS_FAN7_PRSNT_D_N";
+			gpios = <&gpio ASPEED_GPIO(AB, 1) GPIO_ACTIVE_LOW>;
+			linux,code = <ASPEED_GPIO(AB, 1)>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		// A0-A7
+		BMC_SEL_M2_SATA_PCIE {
+			label = "BMC_SEL_M2_SATA_PCIE";
+			gpios = <&gpio ASPEED_GPIO(A, 0) GPIO_ACTIVE_HIGH>;
+			linux,code = <ASPEED_GPIO(A, 0)>;
+		};
+
+		PD_RMII_BMC_MDC {
+			label = "PD_RMII_BMC_MDC";
+			gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
+			linux,code = <ASPEED_GPIO(A, 6)>;
+		};
+
+		PD_RMII_BMC_MDIO {
+			label = "PD_RMII_BMC_MDIO";
+			gpios = <&gpio ASPEED_GPIO(A, 7) GPIO_ACTIVE_HIGH>;
+			linux,code = <ASPEED_GPIO(A, 7)>;
+		};
+		// B0-B7
+		VR_PVCCIN_PVCCSA_CPU1_FAULT_N {
+			label = "VR_PVCCIN_PVCCSA_CPU1_FAULT_N";
+			gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>;
+			linux,code = <ASPEED_GPIO(B, 0)>;
+		};
+
+		VR_PVCCIN_PVCCSA_CPU2_FAULT_N {
+			label = "VR_PVCCIN_PVCCSA_CPU2_FAULT_N";
+			gpios = <&gpio ASPEED_GPIO(B, 1) GPIO_ACTIVE_LOW>;
+			linux,code = <ASPEED_GPIO(B, 1)>;
+		};
+
+		VR_PVCCIO_CPU1_FAULT_N {
+			label = "VR_PVCCIO_CPU1_FAULT_N";
+			gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>;
+			linux,code = <ASPEED_GPIO(B, 2)>;
+		};
+
+		VR_PVCCIO_CPU2_FAULT_N {
+			label = "VR_PVCCIO_CPU2_FAULT_N";
+			gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>;
+			linux,code = <ASPEED_GPIO(B, 3)>;
+		};
+
+		NC_CLK_48M_USB_NMC_R2 {
+			label = "NC_CLK_48M_USB_NMC_R2";
+			gpios = <&gpio ASPEED_GPIO(B, 4) GPIO_ACTIVE_HIGH>;
+			linux,code = <ASPEED_GPIO(B, 4)>;
+		};
+
+		PU_BMC_GPIOB6 {
+			label = "PU_BMC_GPIOB6";
+			gpios = <&gpio ASPEED_GPIO(B, 6) GPIO_ACTIVE_HIGH>;
+			linux,code = <ASPEED_GPIO(B, 6)>;
+		};
+
+		NC_BMC_GPIOB7 {
+			label = "NC_BMC_GPIOB7";
+			gpios = <&gpio ASPEED_GPIO(B, 7) GPIO_ACTIVE_HIGH>;
+			linux,code = <ASPEED_GPIO(B, 7)>;
+		};
+		// C0-C7
+		PROJECT_REV_ID0 {
+			label = "PROJECT_REV_ID0";
+			gpios = <&gpio ASPEED_GPIO(C, 0) GPIO_ACTIVE_HIGH>;
+			linux,code = <ASPEED_GPIO(C, 0)>;
+		};
+
+		PROJECT_REV_ID1 {
+			label = "PROJECT_REV_ID1";
+			gpios = <&gpio ASPEED_GPIO(C, 1) GPIO_ACTIVE_HIGH>;
+			linux,code = <ASPEED_GPIO(C, 1)>;
+		};
+
+		PROJECT_REV_ID2 {
+			label = "PROJECT_REV_ID2";
+			gpios = <&gpio ASPEED_GPIO(C, 2) GPIO_ACTIVE_HIGH>;
+			linux,code = <ASPEED_GPIO(C, 2)>;
+		};
+
+		PCB_REV_ID0 {
+			label = "PCB_REV_ID0";
+			gpios = <&gpio ASPEED_GPIO(C, 3) GPIO_ACTIVE_HIGH>;
+			linux,code = <ASPEED_GPIO(C, 3)>;
+		};
+
+		PCB_REV_ID1 {
+			label = "PCB_REV_ID1";
+			gpios = <&gpio ASPEED_GPIO(C, 4) GPIO_ACTIVE_HIGH>;
+			linux,code = <ASPEED_GPIO(C, 4)>;
+		};
+
+		PCB_REV_ID2 {
+			label = "PCB_REV_ID2";
+			gpios = <&gpio ASPEED_GPIO(C, 5) GPIO_ACTIVE_HIGH>;
+			linux,code = <ASPEED_GPIO(C, 5)>;
+		};
+
+		NC_BMC_GPIOC6 {
+			label = "NC_BMC_GPIOC6";
+			gpios = <&gpio ASPEED_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
+			linux,code = <ASPEED_GPIO(C, 6)>;
+		};
+
+		NC_BMC_GPIOC7 {
+			label = "NC_BMC_GPIOC7";
+			gpios = <&gpio ASPEED_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
+			linux,code = <ASPEED_GPIO(C, 7)>;
+		};
+		// D0-D7
+		FM_FORCE_BMC_UPDATE_N {
+			label = "FM_FORCE_BMC_UPDATE_N";
+			gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_LOW>;
+			linux,code = <ASPEED_GPIO(D, 0)>;
+		};
+
+		RST_RSTB_BMC_R_N {
+			label = "RST_RSTB_BMC_R_N";
+			gpios = <&gpio ASPEED_GPIO(D, 1) GPIO_ACTIVE_LOW>;
+			linux,code = <ASPEED_GPIO(D, 1)>;
+		};
+
+		NC_BMC_GPIOD2 {
+			label = "NC_BMC_GPIOD2";
+			gpios = <&gpio ASPEED_GPIO(D, 2) GPIO_ACTIVE_HIGH>;
+			linux,code = <ASPEED_GPIO(D, 2)>;
+		};
+
+		NC_BMC_GPIOD3 {
+			label = "NC_BMC_GPIOD3";
+			gpios = <&gpio ASPEED_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
+			linux,code = <ASPEED_GPIO(D, 3)>;
+		};
+
+		NC_BMC_GPIOD4 {
+			label = "NC_BMC_GPIOD4";
+			gpios = <&gpio ASPEED_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
+			linux,code = <ASPEED_GPIO(D, 4)>;
+		};
+
+		NC_BMC_GPIOD5 {
+			label = "NC_BMC_GPIOD5";
+			gpios = <&gpio ASPEED_GPIO(D, 5) GPIO_ACTIVE_HIGH>;
+			linux,code = <ASPEED_GPIO(D, 5)>;
+		};
+	};
+
+};
+
+
+&gpio {
+	// A0-A7
+	fm_spd_ddrcpu_lvlshft_en_r {
+		gpio-hog;
+		label = "FM_SPD_DDRCPU_LVLSHFT_EN_R";
+		gpios = <ASPEED_GPIO(A, 1) GPIO_ACTIVE_HIGH>;
+		linux,code = <ASPEED_GPIO(A, 1)>;
+		output-high;
+	};
+
+	mb_bmc_hbsp_reset_n {
+		gpio-hog;
+		label = "MB_BMC_HBSP_RESET_N";
+		gpios = <ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;
+		linux,code = <ASPEED_GPIO(A, 2)>;
+		output-high;
+	};
+
+	mb_bmc_hbsp_isp_n {
+		gpio-hog;
+		label = "MB_BMC_HBSP_ISP_N";
+		gpios = <ASPEED_GPIO(A, 3) GPIO_ACTIVE_LOW>;
+		linux,code = <ASPEED_GPIO(A, 3)>;
+		output-high;
+	};
+	// D0-D7
+	jtag_pld_en {
+		gpio-hog;
+		label = "JTAG_PLD_EN";
+		gpios = <ASPEED_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
+		linux,code = <ASPEED_GPIO(D, 6)>;
+		output-low;
+	};
+	FM_BMC_DBP_PRESENT_R_N {
+		gpio-hog;
+		label = "FM_BMC_DBP_PRESENT_R_N";
+		gpios = <ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>;
+		linux,code = <ASPEED_GPIO(E, 5)>;
+		output-high;
+	};
+
+	// F0-F7
+	IRQ_BMC_PCH_NMI_R {
+		gpio-hog;
+		label = "IRQ_BMC_PCH_NMI_R";
+		gpios = <ASPEED_GPIO(F, 0) GPIO_ACTIVE_HIGH>;
+		linux,code = <ASPEED_GPIO(F, 0)>;
+		output-low;
+	};
+
+	FM_CPU2_DISABLE_COD_N {
+		gpio-hog;
+		label = "FM_CPU2_DISABLE_COD_N";
+		gpios = <ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>;
+		linux,code = <ASPEED_GPIO(F, 1)>;
+		output-high;
+	};
+
+	SPI_SYSBIOS_BMC_SEL {
+		gpio-hog;
+		label = "SPI_SYSBIOS_BMC_SEL";
+		gpios = <ASPEED_GPIO(F, 2) GPIO_ACTIVE_LOW>;
+		linux,code = <ASPEED_GPIO(F, 2)>;
+		output-high;
+	};
+	// Q0-Q7
+	FM_BMC_CPU_PWR_DEBUG_R_N {
+		gpio-hog;
+		label = "FM_BMC_CPU_PWR_DEBUG_R_N";
+		gpios = <ASPEED_GPIO(Q, 7) GPIO_ACTIVE_LOW>;
+		linux,code = <ASPEED_GPIO(Q, 7)>;
+		output-high;
+	};
+};
+
+
+&fmc {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
+		label = "bmc";
+		spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout.dtsi"
+	};
+};
+
+&spi1 {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
+		label = "pnor";
+		spi-max-frequency = <100000000>;
+	};
+};
+
+&spi2 {
+	status = "okay";
+};
+
+&uart5 {
+	status = "okay";
+};
+
+&mac0 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>;
+};
+
+&mac1 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
+};
+
+&adc {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+
+	eeprom@54 {
+        compatible = "atmel,24c64";
+        reg = <0x54>;
+        pagesize = <32>;
+    };
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+
+	tmp75@48 {
+		compatible = "ti,tmp75";
+		reg = <0x48>;
+	};	
+
+	tmp75@4b {
+		compatible = "ti,tmp75";
+		reg = <0x4b>;
+	};	
+
+	tmp75@4c {
+		compatible = "ti,tmp75";
+		reg = <0x4c>;
+	};
+
+	tmp75@4d {
+		compatible = "ti,tmp75";
+		reg = <0x4d>;
+	};
+
+	vr-controller@5a {
+		compatible = "ti,tps53679";
+		reg = <0x5a>;
+	};	
+
+	vr-controller@5d {
+		compatible = "ti,tps53679";
+		reg = <0x5d>;
+	};	
+
+	vr-controller@68 {
+		compatible = "ti,tps53679";
+		reg = <0x68>;
+	};	
+
+	vr-controller@6a {
+		compatible = "ti,tps53679";
+		reg = <0x6a>;
+	};	
+	
+	vr-controller@6c {
+		compatible = "ti,tps53679";
+		reg = <0x6c>;
+	};	
+	
+	vr-controller@6e {
+		compatible = "ti,tps53679";
+		reg = <0x6e>;
+	};	
+
+};
+
+&i2c4 {
+	status = "okay";
+
+	eeprom@51 {
+        compatible = "atmel,24c64";
+        reg = <0x51>;
+        pagesize = <32>;
+    };
+};
+
+&i2c5 {
+	status = "okay";
+};
+
+&i2c6 {
+	status = "okay";
+};
+
+&i2c7 {
+	status = "okay";
+	
+	power-supply@58 {
+		compatible = "pmbus";
+		reg = <0x58>;
+	};
+
+	power-supply@59 {
+		compatible = "pmbus";
+		reg = <0x59>;
+	};
+};
+
+
+&sdmmc {
+	status = "okay";
+};
+
+&sdhci0 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sd1_default>;
+};
+
+/*
+ * Enable port A as device (via the virtual hub) and port B as
+ * host by default on the eval board. This can be easily changed
+ * by replacing the override below with &ehci0 { ... } to enable
+ * host on both ports.
+ */
+&vhub {
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&uhci {
+	status = "okay";
+};
+
+&gfx {
+     status = "okay";
+     memory-region = <&gfx_memory>;
+};
+
+&pwm_tacho {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
+		&pinctrl_pwm2_default &pinctrl_pwm3_default
+		&pinctrl_pwm4_default &pinctrl_pwm5_default
+		&pinctrl_pwm6_default &pinctrl_pwm7_default>;
+
+	fan@0 {
+		reg = <0x00>;
+		aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>;
+	};
+
+	fan@1 {
+		reg = <0x01>;
+		aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>;
+	};
+
+	fan@2 {
+		reg = <0x02>;
+		aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>;
+	};
+
+	fan@3 {
+		reg = <0x03>;
+		aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>;
+	};
+
+	fan@4 {
+		reg = <0x04>;
+		aspeed,fan-tach-ch = /bits/ 8 <0x08 0x09>;
+	};
+
+	fan@5 {
+		reg = <0x05>;
+		aspeed,fan-tach-ch = /bits/ 8 <0x0a 0x0b>;
+	};
+
+	fan@6 {
+		reg = <0x06>;
+		aspeed,fan-tach-ch = /bits/ 8 <0x0c 0x0d>;
+	};
+
+	fan@7 {
+		reg = <0x07>;
+		aspeed,fan-tach-ch = /bits/ 8 <0x0e 0x0f>;
+	};
+
+};
+
-- 
2.7.4


             reply	other threads:[~2021-01-07 22:55 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-07  3:41 Willie Thai [this message]
2021-01-08  3:12 ` [PATCH] ARM: dts: aspeed: Add device tree for Liwu2 BMC Joel Stanley
2021-01-11  9:42   ` Willie Thai
2021-02-09 12:25     ` Joel Stanley
2021-02-19  7:11       ` [[PATCH linux dev-5.8] ARM: dts: Aspeed: Add Compal's Liwu2 BMC machine] ARM: dts: aspeed: Add device tree for Compal's " Willie Thai
2021-03-31  6:33         ` Joel Stanley
2021-04-01  0:31         ` Andrew Jeffery
2021-08-20  2:36           ` [External Mail] Willie_Thai

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