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X-ME-Sender: Received: from localhost.localdomain (ppp118-210-173-37.bras2.adl6.internode.on.net [118.210.173.37]) by mail.messagingengine.com (Postfix) with ESMTPA id 72C7CE473B; Wed, 11 Jul 2018 01:32:26 -0400 (EDT) From: Andrew Jeffery To: linux-kernel@vger.kernel.org Cc: Andrew Jeffery , robh+dt@kernel.org, mark.rutland@arm.com, joel@jms.id.au, gregkh@linuxfoundation.org, Eugene.Cho@dell.com, a.amelkin@yadro.com, stewart@linux.ibm.com, benh@kernel.crashing.org, openbmc@lists.ozlabs.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH v2 4/4] dts: aspeed-g5: Describe VGA, SIO scratch and DAC mux fields Date: Wed, 11 Jul 2018 15:01:22 +0930 Message-Id: <20180711053122.30773-5-andrew@aj.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180711053122.30773-1-andrew@aj.id.au> References: <20180711053122.30773-1-andrew@aj.id.au> X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jul 2018 05:32:34 -0000 The AST2500 has VGA scratch registers that are read-only, SuperIO scratch registers that are a mix of read-only and read-write, and a graphics DAC mux that must be read or configured in the process of booting e.g. an OpenPOWER system. These capabilities do not really have a place in other drivers, so expose them as fields via bmc-misc-ctrl. Signed-off-by: Andrew Jeffery --- Since RFC v1: * Rework labels to what is documented in the bindings * Fix an incorrect offset property arch/arm/boot/dts/aspeed-g5.dtsi | 192 +++++++++++++++++++++++++++++++ 1 file changed, 192 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 17f2714d18a7..c484ac637328 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -187,6 +187,77 @@ aspeed,external-nodes = <&gfx &lhc>; }; + + field@2c.16 { + compatible = "bmc-misc-ctrl"; + offset = <0x2c>; + mask = <0x00030000>; + label = "dac-mux"; + }; + + field@50.0 { + compatible = "bmc-misc-ctrl"; + offset = <0x50>; + mask = <0xffffffff>; + label = "vga0"; + read-only; + }; + + field@54.0 { + compatible = "bmc-misc-ctrl"; + offset = <0x54>; + mask = <0xffffffff>; + label = "vga1"; + read-only; + }; + + field@58.0 { + compatible = "bmc-misc-ctrl"; + offset = <0x58>; + mask = <0xffffffff>; + label = "vga2"; + read-only; + }; + + field@5c.0 { + compatible = "bmc-misc-ctrl"; + offset = <0x5c>; + mask = <0xffffffff>; + label = "vga3"; + read-only; + }; + + field@60.0 { + compatible = "bmc-misc-ctrl"; + offset = <0x60>; + mask = <0xffffffff>; + label = "vga4"; + read-only; + }; + + field@64.0 { + compatible = "bmc-misc-ctrl"; + offset = <0x64>; + mask = <0xffffffff>; + label = "vga5"; + read-only; + }; + + field@68.0 { + compatible = "bmc-misc-ctrl"; + offset = <0x68>; + mask = <0xffffffff>; + label = "vga6"; + read-only; + }; + + field@6c.0 { + compatible = "bmc-misc-ctrl"; + offset = <0x6c>; + mask = <0xffffffff>; + label = "vga7"; + read-only; + }; }; rng: hwrng@1e6e2078 { @@ -343,6 +414,127 @@ #reset-cells = <1>; }; + field@f0.24 { + compatible = "bmc-misc-ctrl"; + offset = <0xf0>; + mask = <0xff000000>; + label = "sio2b"; + }; + + field@f0.16 { + compatible = "bmc-misc-ctrl"; + offset = <0xf0>; + mask = <0x00ff0000>; + label = "sio2a"; + }; + + field@f0.8 { + compatible = "bmc-misc-ctrl"; + offset = <0xf0>; + mask = <0x0000ff00>; + bit-shift = <8>; + label = "sio29"; + }; + + field@f0.0 { + compatible = "bmc-misc-ctrl"; + offset = <0xf0>; + mask = <0x000000ff>; + label = "sio28"; + }; + + field@f4.24 { + compatible = "bmc-misc-ctrl"; + offset = <0xf4>; + mask = <0xff000000>; + label = "sio2f"; + }; + + field@f4.16 { + compatible = "bmc-misc-ctrl"; + offset = <0xf4>; + mask = <0x00ff0000>; + label = "sio2e"; + }; + + field@f4.8 { + compatible = "bmc-misc-ctrl"; + offset = <0xf4>; + mask = <0x0000ff00>; + label = "sio2d"; + }; + + field@f4.0 { + compatible = "bmc-misc-ctrl"; + offset = <0xf4>; + mask = <0x000000ff>; + label = "sio2c"; + }; + + field@f8.24 { + compatible = "bmc-misc-ctrl"; + offset = <0xf8>; + mask = <0xff000000>; + read-only; + label = "sio23"; + }; + + field@f8.16 { + compatible = "bmc-misc-ctrl"; + offset = <0xf8>; + mask = <0x00ff0000>; + read-only; + label = "sio22"; + }; + + field@f8.8 { + compatible = "bmc-misc-ctrl"; + offset = <0xf8>; + mask = <0x0000ff00>; + read-only; + label = "sio21"; + }; + + field@f8.0 { + compatible = "bmc-misc-ctrl"; + offset = <0xf8>; + mask = <0x000000ff>; + read-only; + label = "sio20"; + }; + + field@fc.24 { + compatible = "bmc-misc-ctrl"; + offset = <0xfc>; + mask = <0xff000000>; + read-only; + label = "sio27"; + }; + + field@fc.16 { + compatible = "bmc-misc-ctrl"; + offset = <0xfc>; + mask = <0x00ff0000>; + read-only; + label = "sio26"; + }; + + field@fc.8 { + compatible = "bmc-misc-ctrl"; + offset = <0xfc>; + mask = <0x0000ff00>; + read-only; + label = "sio25"; + }; + + field@fc.0 { + compatible = "bmc-misc-ctrl"; + offset = <0xfc>; + mask = <0x000000ff>; + read-only; + label = "sio24"; + }; + ibt: ibt@c0 { compatible = "aspeed,ast2500-ibt-bmc"; reg = <0xc0 0x18>; -- 2.17.1