From: Wolfram Sang <wsa@kernel.org>
To: Tali Perry <tali.perry1@gmail.com>
Cc: benjaminfair@google.com, avifishman70@gmail.com,
openbmc@lists.ozlabs.org, linux-kernel@vger.kernel.org,
linux-i2c@vger.kernel.org, andriy.shevchenko@linux.intel.com,
tmaimon77@gmail.com
Subject: Re: [PATCH v1] i2c: npcm7xx: Clear LAST bit after a failed transaction.
Date: Sun, 27 Sep 2020 20:06:16 +0200 [thread overview]
Message-ID: <20200927180616.GG19475@kunai> (raw)
In-Reply-To: <20200920204809.132911-1-tali.perry1@gmail.com>
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On Sun, Sep 20, 2020 at 11:48:09PM +0300, Tali Perry wrote:
> Due to a HW issue, in some scenarios the LAST bit might remain set.
> This will cause an unexpected NACK after reading 16 bytes on the next
> read.
>
> Example: if user tries to read from a missing device, get a NACK,
> then if the next command is a long read ( > 16 bytes),
> the master will stop reading after 16 bytes.
> To solve this, if a command fails, check if LAST bit is still
> set. If it does, reset the module.
>
> Fixes: 56a1485b102e (i2c: npcm7xx: Add Nuvoton NPCM I2C controller driver)
> Signed-off-by: Tali Perry <tali.perry1@gmail.com>
Applied to for-current, thanks!
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prev parent reply other threads:[~2020-09-28 2:08 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-20 20:48 [PATCH v1] i2c: npcm7xx: Clear LAST bit after a failed transaction Tali Perry
2020-09-27 18:06 ` Wolfram Sang [this message]
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