From: "Chia-Wei, Wang" <chiawei_wang@aspeedtech.com>
To: <lee.jones@linaro.org>, <robh+dt@kernel.org>, <joel@jms.id.au>,
<andrew@aj.id.au>, <minyard@acm.org>, <arnd@arndb.de>,
<gregkh@linuxfoundation.org>, <linus.walleij@linaro.org>,
<haiyue.wang@linux.intel.com>, <cyrilbur@gmail.com>,
<rlippert@google.com>, <linux-arm-kernel@lists.infradead.org>,
<linux-aspeed@lists.ozlabs.org>, <linux-kernel@vger.kernel.org>,
<openbmc@lists.ozlabs.org>, <linux-gpio@vger.kernel.org>
Cc: ryan_chen@aspeedtech.com
Subject: [PATCH v2 2/5] soc: aspeed: Fix LPC register offsets
Date: Mon, 5 Oct 2020 16:28:03 +0800 [thread overview]
Message-ID: <20201005082806.28899-3-chiawei_wang@aspeedtech.com> (raw)
In-Reply-To: <20201005082806.28899-1-chiawei_wang@aspeedtech.com>
The LPC register offsets are fixed to adapt to the LPC DTS change,
where the LPC partitioning is removed.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
---
drivers/soc/aspeed/aspeed-lpc-ctrl.c | 6 +++---
drivers/soc/aspeed/aspeed-lpc-snoop.c | 11 +++++------
2 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/soc/aspeed/aspeed-lpc-ctrl.c b/drivers/soc/aspeed/aspeed-lpc-ctrl.c
index 01ed21e8bfee..36faa0618ada 100644
--- a/drivers/soc/aspeed/aspeed-lpc-ctrl.c
+++ b/drivers/soc/aspeed/aspeed-lpc-ctrl.c
@@ -17,12 +17,12 @@
#define DEVICE_NAME "aspeed-lpc-ctrl"
-#define HICR5 0x0
+#define HICR5 0x80
#define HICR5_ENL2H BIT(8)
#define HICR5_ENFWH BIT(10)
-#define HICR7 0x8
-#define HICR8 0xc
+#define HICR7 0x88
+#define HICR8 0x8c
struct aspeed_lpc_ctrl {
struct miscdevice miscdev;
diff --git a/drivers/soc/aspeed/aspeed-lpc-snoop.c b/drivers/soc/aspeed/aspeed-lpc-snoop.c
index f3d8d53ab84d..7ce5c9fcc73c 100644
--- a/drivers/soc/aspeed/aspeed-lpc-snoop.c
+++ b/drivers/soc/aspeed/aspeed-lpc-snoop.c
@@ -28,26 +28,25 @@
#define NUM_SNOOP_CHANNELS 2
#define SNOOP_FIFO_SIZE 2048
-#define HICR5 0x0
+#define HICR5 0x80
#define HICR5_EN_SNP0W BIT(0)
#define HICR5_ENINT_SNP0W BIT(1)
#define HICR5_EN_SNP1W BIT(2)
#define HICR5_ENINT_SNP1W BIT(3)
-
-#define HICR6 0x4
+#define HICR6 0x84
#define HICR6_STR_SNP0W BIT(0)
#define HICR6_STR_SNP1W BIT(1)
-#define SNPWADR 0x10
+#define SNPWADR 0x90
#define SNPWADR_CH0_MASK GENMASK(15, 0)
#define SNPWADR_CH0_SHIFT 0
#define SNPWADR_CH1_MASK GENMASK(31, 16)
#define SNPWADR_CH1_SHIFT 16
-#define SNPWDR 0x14
+#define SNPWDR 0x94
#define SNPWDR_CH0_MASK GENMASK(7, 0)
#define SNPWDR_CH0_SHIFT 0
#define SNPWDR_CH1_MASK GENMASK(15, 8)
#define SNPWDR_CH1_SHIFT 8
-#define HICRB 0x80
+#define HICRB 0x100
#define HICRB_ENSNP0D BIT(14)
#define HICRB_ENSNP1D BIT(15)
--
2.17.1
next prev parent reply other threads:[~2020-10-05 8:31 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-05 8:28 [PATCH v2 0/5] Remove LPC register partitioning Chia-Wei, Wang
2020-10-05 8:28 ` [PATCH v2 1/5] ARM: dts: Remove LPC BMC and Host partitions Chia-Wei, Wang
2020-10-05 8:28 ` Chia-Wei, Wang [this message]
2020-10-05 8:28 ` [PATCH v2 3/5] ipmi: kcs: aspeed: Fix LPC register offsets Chia-Wei, Wang
2020-10-05 8:28 ` [PATCH v2 4/5] pinctrl: aspeed-g5: " Chia-Wei, Wang
2020-10-05 8:28 ` [PATCH v2 5/5] dt-bindings: aspeed-lpc: Remove LPC partitioning Chia-Wei, Wang
2020-10-26 3:12 ` Andrew Jeffery
2020-10-27 7:14 ` ChiaWei Wang
2020-12-14 2:44 ` ChiaWei Wang
2020-12-15 0:12 ` Andrew Jeffery
2020-12-15 2:17 ` ChiaWei Wang
2020-10-20 6:03 ` [PATCH v2 0/5] Remove LPC register partitioning ChiaWei Wang
2020-10-26 2:45 ` Andrew Jeffery
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